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1. 发明申请

WO2017074648A1 TEMPERATURE DEPENDENT MULTIPLE MODE ERROR CORRECTION 审中-公开
标题翻译：温度相关的多模式误差校正
公开(公告)号：WO2017074648A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/055033
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： WU, Wei , AUGUSTINE, Charles , TOMISHIMA, Shigeki , LU, Shih-Lien L. , TSCHANZ, James W.
IPC分类号： G06F11/10
CPC分类号： H03M13/05 , G06F11/1048 , H03M13/1515 , H03M13/353 , H03M13/611
摘要： In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.
摘要翻译：在一个实施例中，根据本公开的一个方面的温度相关的多模式误差校正被用于包含存储器单元阵列的存储器电路。在一个实施例中，耦合到阵列的温度传感器被配置为提供输出信号，该输出信号是存储器单元阵列的温度的函数。具有耦合到温度传感器的输出的输入的多模式错误校正码（ECC）逻辑被配置为对错误校正码中的存储器单元阵列的读取数据进行编码写入数据和解码读取数据，其中多个错误校正模式作为存储器单元阵列的温度的函数。其他方面在这里描述。

2. 发明申请

WO2015023290A1 MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY 审中-公开
标题翻译：使用电阻记忆的记忆单元
公开(公告)号：WO2015023290A1
公开(公告)日：2015-02-19
申请号：PCT/US2013/055332
申请日：2013-08-16
申请人： AUGUSTINE, Charles , TOKUNAGA, Carlos , TSCHANZ, James W. , INTEL CORPORATION
发明人： AUGUSTINE, Charles , TOKUNAGA, Carlos , TSCHANZ, James W.
IPC分类号： G11C11/41 , H04L25/18
CPC分类号： G11C14/0081 , G11C11/1697 , G11C13/0011 , G11C14/0072 , G11C14/009
摘要： Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: a memory element including cross-coupled cells having a first node and a second node; a first transistor coupled to the first node; a second transistor coupled to the second node; and a resistive memory element coupled to the first and second transistors.
摘要翻译：描述了一种包括使用电阻性存储器保持的存储单元的装置。该装置包括：存储元件，其包括具有第一节点和第二节点的交叉耦合小区; 耦合到所述第一节点的第一晶体管; 耦合到所述第二节点的第二晶体管; 以及耦合到第一和第二晶体管的电阻性存储元件。

3. 发明申请

WO2018005004A1 PHYSICALLY UNCLONABLE FUNCTION CIRCUIT INCLUDING MEMORY ELEMENTS 审中-公开
标题翻译：包含存储器元件的物理无关函数电路
公开(公告)号：WO2018005004A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035786
申请日：2017-06-02
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , KUMAR, Suriya Ashok , TOKUNAGA, Carlos , TSCHANZ, James W.
IPC分类号： G06F21/71
CPC分类号： H03K19/00315 , H03K3/0315 , H03K3/84 , H03K19/1776 , H04L9/3278
摘要： Some embodiments include apparatus and methods using a first ring oscillator, a second ring oscillator, and circuit coupled to the first and second ring oscillators. The first ring oscillator includes a first memory cell and a first plurality of stages coupled to the first memory cell. The second ring oscillator includes a second memory cell and a second plurality of stages coupled to the second memory cell. The circuit includes a first input node coupled to an output node of the first ring oscillator and a second input node coupled to an output node of the second ring oscillator. In one of such embodiments, the circuit can operate to generate identification information to authenticate the apparatus.
摘要翻译：一些实施例包括使用第一环形振荡器，第二环形振荡器和耦合到第一环形振荡器和第二环形振荡器的电路的设备和方法。第一环形振荡器包括第一存储器单元和耦合到第一存储器单元的第一多个级。第二环形振荡器包括第二存储器单元和耦合到第二存储器单元的第二多个级。该电路包括耦合到第一环形振荡器的输出节点的第一输入节点和耦合到第二环形振荡器的输出节点的第二输入节点。在这样的实施例中的一个中，电路可以操作以生成识别信息以认证该装置。

4. 发明申请

WO2016209393A1 MAGNETIC STORAGE CELL MEMORY WITH BACK-HOP PREVENTION 审中-公开
标题翻译：具有背部预防功能的磁性存储单元存储器
公开(公告)号：WO2016209393A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/031895
申请日：2016-05-11
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , TOMISHIMA, Shigeki , WU, Wei , LU, Shih-Lien , TSCHANZ, James W. , PANAGOPOULOS, Georgios , NAEIMI, Helia
IPC分类号： G11C11/16 , H01L27/22 , H01L43/08
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1677 , G11C11/1693 , G11C11/1697
摘要： An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
摘要翻译：描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。该装置还包括用于迭代地写入一个或多个比特位置的电路，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。

5. 发明申请

WO2013085499A1 LOW POWER VOICE DETECTION 审中-公开
标题翻译：低功率语音检测
公开(公告)号：WO2013085499A1
公开(公告)日：2013-06-13
申请号：PCT/US2011/063622
申请日：2011-12-06
申请人： INTEL CORPORATION , RAYCHOWDHURY, Arijit , BELTMAN, Willem M. , TSCHANZ, James W. , TOKUNAGA, Carlos , DEISHER, Michael E. , WALSH, Thomas E.
发明人： RAYCHOWDHURY, Arijit , BELTMAN, Willem M. , TSCHANZ, James W. , TOKUNAGA, Carlos , DEISHER, Michael E. , WALSH, Thomas E.
IPC分类号： G10L19/00 , G10L11/00
CPC分类号： G10L15/20 , G06F1/3234 , G06F17/142 , G10L15/22 , G10L15/285 , G10L21/0208 , G10L21/0232 , G10L25/18 , G10L25/84 , G10L2015/223 , G10L2021/02087
摘要： Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
摘要翻译：以最小功耗实现语音处理的方法包括以第一时钟频率和第一电压记录时域音频信号，并且以第二时钟频率对时域音频信号执行快速傅立叶变换（FFT）操作以产生频率域音频信号。可以通过一个或多个滤波和增强技术来增强频域音频信号以获得更好的信噪比。增强音频信号可用于产生总信号能量并估计背景噪声能量。决策逻辑可以根据信号能量和背景噪声来确定人类语音的存在或不存在。第一时钟频率可以不同于第二时钟频率。

6. 发明公开

EP3084916A1 APPARATUS FOR CHARGE RECOVERY DURING LOW POWER MODE 审中-公开
标题翻译：设备，用于低功率模式，充电恢复
公开(公告)号：EP3084916A1
公开(公告)日：2016-10-26
申请号：EP13899423.1
申请日：2013-12-20
申请人： Intel Corporation
发明人： KULKARNI, Jaydeep P. , MEINERZHAGEN, Pascal A. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： H02J7/00
CPC分类号： H02M3/073 , G06F3/041 , H02J7/00 , H03K3/0377 , H03K19/21
摘要： Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

7. 发明申请

WO2015094374A1 APPARATUS FOR CHARGE RECOVERY DURING LOW POWER MODE 审中-公开
标题翻译：低功耗模式下充电恢复的装置
公开(公告)号：WO2015094374A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/077277
申请日：2013-12-20
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , MEINERZHAGEN, Pascal A. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： H02J7/00
CPC分类号： H02M3/073 , G06F3/041 , H02J7/00 , H03K3/0377 , H03K19/21
摘要： Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
摘要翻译：描述了一种用于电源管理的设备。该装置包括：第一电源节点; 第二电源节点; 耦合到所述第一电源节点和所述第二电源节点的可控设备，所述可控设备可操作以将所述第一电源节点缩短到所述第二电源节点; 耦合到所述第二电源节点的负载; 以及耦合到第一和第二电源节点的电荷恢复泵（CRP）。

8. 发明申请

WO2014022029A1 INTEGRATED NON-VOLATILE MONOTONIC COUNTERS 审中-公开
标题翻译：集成非易失性单体计数器
公开(公告)号：WO2014022029A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/047868
申请日：2013-06-26
申请人： INTEL CORPORATION
发明人： TSCHANZ, James W. , WILKERSON, Christopher B. , ROBINSON, Scott , LU, Shih-Lien
IPC分类号： G06F21/00
CPC分类号： H03K21/023 , H03K21/12
摘要： Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.
摘要翻译：一些实施例包括具有第一发生器以产生具有不同频率的信号的计数器，以及产生计数器的计数器值的第二发生器。每个计数器值可以至少部分地基于信号中相应信号的转换的数量。描述其他实施例。

9. 发明申请

WO2014004011A1 APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY 审中-公开
标题翻译：用于减少存储器的最小供电电压的装置
公开(公告)号：WO2014004011A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/044362
申请日：2013-06-05
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , KHELLAH, Muhammad M. , TSCHANZ, James W. , GEUSKENS, Bibiche M. , DE, Vivek K.
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C11/419 , G11C7/227 , G11C11/412 , G11C11/413
摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
摘要翻译：描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到所述第一供应节点和第二供应节点的功率设备，所述第二供应节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平操作。

10. 发明申请

WO2013089698A1 MULTI-SUPPLY SEQUENTIAL LOGIC UNIT 审中-公开
标题翻译：多供应序列逻辑单元
公开(公告)号：WO2013089698A1
公开(公告)日：2013-06-20
申请号：PCT/US2011/064848
申请日：2011-12-14
申请人： INTEL CORPORATION , RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
发明人： RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
IPC分类号： G06F1/04 , G06F1/26
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。所述装置包括顺序单元，包括：数据路径，用于接收包括在第一电源电平上操作的逻辑门的输入信号，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力供应水平。该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

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