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1. 发明申请

WO2017105669A1 WARPAGE CONTROLLED PACKAGE AND METHOD FOR SAME 审中-公开
标题翻译：翘曲控制包装及其制造方法
公开(公告)号：WO2017105669A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/060818
申请日：2016-11-07
申请人： INTEL CORPORATION
发明人： KUMAR, Siddarth , SANE, Sandeep B. , SAHASRABUDHE, Shubhada H. , TANDON, Shalabh
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L23/562 , H01L23/16 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/131 , H01L2224/16227 , H01L2224/81815 , H01L2924/15311 , H01L2924/3511 , H01L2924/014 , H01L2924/00014
摘要： A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
摘要翻译：经向控制的包装包括根据热量施加呈现翘曲构型的基底。至少有一个装置沿着衬底耦合。多个电触点至少在器件和衬底之间延伸。一个或多个反力矩元件与衬底耦合。一个或多个计数器时刻元件包括被动配置和计数器时刻配置。在逆时刻配置中，一个或多个反力矩元件被配置为向衬底施加反作用力矩以抵消扭曲配置。在被动配置中，一个或多个反力矩元件被配置为施加小于反力矩配置的反力矩的中性反力矩。

2. 发明申请

WO2017083015A1 PACKAGE ON PACKAGE THROUGH MOLD INTERCONNECTS 审中-公开
标题翻译：通过模具互连进行封装
公开(公告)号：WO2017083015A1
公开(公告)日：2017-05-18
申请号：PCT/US2016/053083
申请日：2016-09-22
申请人： INTEL CORPORATION
发明人： SAHASRABUDHE, Shubhada H. , SANE, Sandeep B. , KUMAR, Siddarth , TANDON, Shalabh
IPC分类号： H01L25/10 , H01L23/00 , H01L23/488
CPC分类号： H01L25/0657 , H01L21/565 , H01L23/3107 , H01L23/3128 , H01L23/49811 , H01L23/49833 , H01L23/5389 , H01L24/17 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/16055 , H01L2224/16057 , H01L2224/1607 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81193 , H01L2224/81365 , H01L2224/81815 , H01L2224/81951 , H01L2225/06513 , H01L2225/06527 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815
摘要： Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
摘要翻译：这里通常讨论的是用于通过模具互连（TMI）更可靠地封装（PoP）封装的方法和设备。器件可以包括第一管芯封装和第二管芯封装，第一管芯封装包括在第一管芯封装上或者至少部分地在第一管芯封装中的第一导电焊盘，在第一管芯封装上的电介质模制材料，模制材料包括穿过其中的至少部分地暴露焊盘的孔，包括在第二管芯上或至少部分地在第二管芯中的第二导电焊盘的管芯封装将第二管芯封装封装在模具材料上，使得第二导电焊盘通过孔面对第一导电焊盘，并且在孔中形成形状记忆结构，第一管芯封装和第二管芯封装之间的焊料柱电连接的一部分。

3. 发明申请

WO2018063213A1 METHODS OF FORMING FLEXURE BASED COOLING SOLUTIONS FOR PACKAGE STRUCTURES 审中-公开
标题翻译：基于柔性基础的包装结构冷却解决方案
公开(公告)号：WO2018063213A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054332
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： KUMAR, Siddarth , SAHASRABUDHE, Shubhada H. , SANE, Sandeep B. , TANDON, Shalabh
IPC分类号： H01L23/367 , H01L23/373 , H01L25/065 , H01L23/00
CPC分类号： H01L23/367 , H01L23/00 , H01L23/3675 , H01L23/4006 , H01L25/065 , H01L2224/16225 , H01L2224/73253
摘要： Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.
摘要翻译：描述了连接封装结构的方法/结构。那些方法/结构可以包括布置在衬底的第一侧上的管芯的第一侧和管芯的第二侧上的冷却结构，其中冷却结构包括附接到衬底的第一部分和布置在衬底的第二侧上的第二部分设置在所述模具的第二侧上，其中所述第一和第二部分通过所述冷却结构中的开口分开。开口围绕第二部分的一部分，并且至少一个挠曲梁结构连接第一和第二部分。

4. 发明申请

WO2017189119A1 MICROELECTRONIC BOND PADS HAVING INTEGRATED SPRING STRUCTURES 审中-公开
标题翻译：具有集成弹簧结构的微电子粘结垫
公开(公告)号：WO2017189119A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/023114
申请日：2017-03-19
申请人： INTEL CORPORATION
发明人： EID, Feras , SANKMAN, Robert L. , SANE, Sandeep B.
IPC分类号： H01L23/488 , H01L23/00
CPC分类号： H01L23/562 , H01L21/485 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L2224/16225 , H01L2924/15311 , H01L2924/3511
摘要： A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
摘要翻译：可以制造微电子封装，其具有至少一个柔性外部接合焊盘，该至少一个柔性外部接合焊盘具有至少一个集成弹簧结构，用于减轻附连到外部基板期间微电子封装的翘曲的影响。用于微电子封装的实施例可以包括具有第一表面和相对的第二表面的微电子封装衬底，其中微电子封装衬底包括限定在其中的空隙，其从第二表面延伸到微电子封装衬底中，并且柔性接合焊盘其中所述柔性接合垫包括接地部分和至少一个弹簧部分，并且其中所述至少一个弹簧部分从所述柔性接合垫接合区部分延伸到所述微电子封装基板第二表面上的锚定结构。 / p>

5. 发明申请

WO2018111249A1 INTEGRATED CIRCUIT PACKAGES WITH PLATES 审中-公开
公开(公告)号：WO2018111249A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066433
申请日：2016-12-14
申请人： INTEL CORPORATION
发明人： KARHADE, Omkar G. , CETEGEN, Edvin , SANE, Sandeep B.
IPC分类号： H01L23/04 , H01L23/10 , H01L23/00 , H01L25/065 , H01L23/498
摘要： Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.

6. 发明申请

WO2018063228A1 METHODS OF UTILIZING LOW TEMPERATURE SOLDER ASSISTED MOUNTING TECHNIQUES FOR PACKAGE STRUCTURES 审中-公开
标题翻译：利用低温焊剂辅助安装技术进行封装结构的方法
公开(公告)号：WO2018063228A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054381
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： KARHADE, Omkar G. , RARAVIKAR, Nachiket R. , SANE, Sandeep B.
IPC分类号： H01L23/00 , H01L23/488 , H01L21/324 , H01L23/12
CPC分类号： H01L23/49816 , H01L23/12 , H01L23/488 , H01L23/562 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/15192 , H01L2924/15311 , H01L2924/3511
摘要： Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.
摘要翻译：描述了连接封装结构的方法/结构。那些方法/结构可以包括设置在衬底的第一侧上的器件和设置在第一衬底的第二侧上的导电互连结构的阵列。阵列的导电互连结构可以包括焊料材料，其中焊料材料包括小于约5％的低温合金元素浓度。第二衬底耦合到导电互连结构阵列。

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