专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2018075052A1 SYSTEMS, APPARATUSES, AND METHODS FOR FUSED MULTIPLY ADD 审中-公开
标题翻译：用于融合乘法加法的系统，装置和方法
公开(公告)号：WO2018075052A1
公开(公告)日：2018-04-26
申请号：PCT/US2016/057991
申请日：2016-10-20
申请人： INTEL CORPORATION
发明人： VALENTINE, Robert , RYVCHIN, Galina , MAJCHER, Piotr , CHARNEY, Mark J. , OULD-AHMED-VALL, Elmoustapha , CORBAL, Jesus , GIRKAR, Milind B. , SPERBER, Zeev , RUBANOVICH, Simon , GRADSTEIN, Amit
IPC分类号： G06F9/30
摘要： I n some embodiments, packed data elements of first and second packed data source operands are of a first, different size than a second size of packed data elements of a third packed data operand. Execution circuitry executes decoded single instruction to perform, for each packed data element position of a destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.
摘要翻译：在一些实施例中，第一和第二打包数据源操作数的打包数据元素具有与第三打包数据操作数的打包数据元素的第二大小不同的第一大小。执行电路执行解码的单个指令以针对目的地操作数的每个打包数据元素位置执行来自第一打包数据源和第二打包数据源的M N个打包数据元素的对应于第三打包数据元素位置的打包数据元素位置将来自这些乘法的结果添加到第三打包数据源的打包数据元素位置的全尺寸打包数据元素，以及将相加结果存储在与打包数据元素对应的打包数据元素位置目的地中第三打包数据源的位置，其中M等于全尺寸打包数据元素除以N。

2. 发明申请

WO2016209582A1 METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR PACKED HISTOGRAM FUNCTIONALITY 审中-公开
标题翻译：方法，装置，说明和逻辑提供矢量包装组织功能
公开(公告)号：WO2016209582A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/035450
申请日：2016-06-02
申请人： INTEL CORPORATION
发明人： GROCHOWSKI, Edward T. , RYVCHIN, Galina , BEHAR, Michael
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F15/8076 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F15/8007
摘要： Instructions and logic provide SIMD vector packed histogram functionality. Some processor embodiments include first and second registers storing, in each of a plurality of data fields of a register lane portion, corresponding elements of a first and of a second data type, respectively. A decode stage decodes an instruction for SIMD vector packed histograms. One or more execution units, compare each element of the first data type, in the first register lane portion, with a range specified by the instruction. For any elements of the first register portion in said range, corresponding elements of the second data type, from the second register portion, are added into one of a plurality data fields of a destination register lane portion, selected according to the value of its corresponding element of the first data type, to generate packed weighted histograms for each destination register lane portion.
摘要翻译：指令和逻辑提供SIMD矢量压缩直方图功能。一些处理器实施例包括分别在寄存器通道部分的多个数据字段的每一个中分别存储第一和第二数据类型的对应元件的第一和第二寄存器。解码级对SIMD矢量压缩直方图的指令进行解码。一个或多个执行单元将第一注册通道部分中的第一数据类型的每个元素与指令指定的范围进行比较。对于所述范围中的第一寄存器部分的任何元件，来自第二寄存器部分的第二数据类型的对应元件被添加到目的地寄存器通道部分的多个数据字段中的一个，根据其相应的值元素，以产生每个目的地寄存器通道部分的压缩的直方图。

3. 发明授权

EP3314407B1 METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR PACKED HISTOGRAM FUNCTIONALITY 有权
公开(公告)号：EP3314407B1
公开(公告)日：2020-11-04
申请号：EP16815015.9
申请日：2016-06-02
申请人： Intel Corporation
发明人： GROCHOWSKI, Edward T. , RYVCHIN, Galina , BEHAR, Michael
IPC分类号： G06F9/30

4. 发明公开

EP3529695A1 SYSTEMS, APPARATUSES, AND METHODS FOR FUSED MULTIPLY ADD 有权
公开(公告)号：EP3529695A1
公开(公告)日：2019-08-28
申请号：EP16919077.4
申请日：2016-10-20
申请人： INTEL Corporation
发明人： VALENTINE, Robert , RYVCHIN, Galina , MAJCHER, Piotr , CHARNEY, Mark J. , OULD-AHMED-VALL, Elmoustapha , CORBAL, Jesus , GIRKAR, Milind B. , SPERBER, Zeev , RUBANOVICH, Simon , GRADSTEIN, Amit
IPC分类号： G06F9/30

5. 发明公开

EP3396624A1 MULTIPLY-ACCUMULATE "0" DATA GATING 审中-公开
公开(公告)号：EP3396624A1
公开(公告)日：2018-10-31
申请号：EP18164095.4
申请日：2018-03-26
申请人： INTEL Corporation
发明人： FAIS, Yaniv , BAR-ON, Tomer , SUBAG, Jacob , DREYFUSS, Jeremie , FAIVISHEVSKY, Lev , BEHAR, Michael , BLEIWEISS, Amit , JACOB, Guy , LEIBOVICH, Gal , BEN-ARI, ltamar , RYVCHIN, Galina , YAACOBY, Eyal
IPC分类号： G06T1/20
CPC分类号： G06F7/5332 , G06N99/005 , G06T1/20
摘要： In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

6. 发明公开

EP3314407A1 METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR PACKED HISTOGRAM FUNCTIONALITY 有权
标题翻译：提供矢量包装直方图功能的方法，装置，指令和逻辑
公开(公告)号：EP3314407A1
公开(公告)日：2018-05-02
申请号：EP16815015.9
申请日：2016-06-02
申请人： Intel Corporation
发明人： GROCHOWSKI, Edward T. , RYVCHIN, Galina , BEHAR, Michael
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F15/8076 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30145 , G06F15/8007
摘要： Instructions and logic provide SIMD vector packed histogram functionality. Some processor embodiments include first and second registers storing, in each of a plurality of data fields of a register lane portion, corresponding elements of a first and of a second data type, respectively. A decode stage decodes an instruction for SIMD vector packed histograms. One or more execution units, compare each element of the first data type, in the first register lane portion, with a range specified by the instruction. For any elements of the first register portion in said range, corresponding elements of the second data type, from the second register portion, are added into one of a plurality data fields of a destination register lane portion, selected according to the value of its corresponding element of the first data type, to generate packed weighted histograms for each destination register lane portion.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式