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1. 发明申请

WO2018004881A1 AN EFFICIENT LOW COST ON-DIE CONFIGURABLE BRIDGE CONTROLLER 审中-公开
标题翻译：一种高效率的低成本可烧结可配置桥控制器
公开(公告)号：WO2018004881A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/034038
申请日：2017-05-23
申请人： INTEL CORPORATION
发明人： BHATT, Suketu U. , PAPPU, Lakshminarayana , CHELLAPPAN, Satheesh
IPC分类号： G06F13/40 , G06F13/10
CPC分类号： G06F13/102 , G06F13/20 , G06F13/4027 , G06F13/4068 , G06F13/4282 , G06F2213/0042
摘要： Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.
摘要翻译：描述了主机接口，设备接口，下游转换电路，上游转换电路和主机线路状态机。主机接口可以包括主机线路状态输出。设备接口可以包括设备线路状态输出。下游翻译电路可以用于处理在主机接口上接收的交易并且为设备接口生成交易。上游翻译电路可以用于处理在设备接口上接收到的交易并且为主接口生成交易。主机线路状态机可以用于将主机线路状态输出设置为以下之一的值：SE0状态值，J状态值或K状态值。

2. 发明申请

WO2017112339A1 SERIAL I/O FUNCTIONAL TESTER 审中-公开
标题翻译：串行I / O功能测试仪
公开(公告)号：WO2017112339A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063781
申请日：2016-11-25
申请人： INTEL CORPORATION
发明人： BHATT, Suketu U. , LEE, Yuen Tat , PAPPU, Lakshminarayana
IPC分类号： G01R31/319 , G01R31/3183
CPC分类号： G06F11/1004 , G01R31/31724 , G06F11/26
摘要： One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol- specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.
摘要翻译：一个实施例提供了一种装置。该设备包括功能测试控制器。功能测试控制器包括控制器逻辑，用于从测试器接收包括分组报头的通信协议专用数据; 协议缓冲区，用于存储数据包报头; 和伪随机比特序列（PRBS）生成器来生成PRBS。控制器逻辑将数据包报头和PRBS组合成数据包，并将数据包提供给被测输入/输出（I / O）控制器。

3. 发明申请

WO2017112219A1 CHIP FABRIC INTERCONNECT QUALITY ON SILICON 审中-公开
标题翻译：硅芯片互连质量
公开(公告)号：WO2017112219A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063122
申请日：2016-11-21
申请人： INTEL CORPORATION
发明人： PAPPU, Lakshminarayana , ADLER, Robert P. , BHATT, Suketu U. , DE GRUIJL, Robert , YEEM, Kah Meng
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3193 , G11C29/56
CPC分类号： G01R31/3177 , H03K19/17704 , H03K19/21
摘要： Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.
摘要翻译：描述的是具有第一组逻辑器件，第二组逻辑器件和存储器件的签名累加器。第一组逻辑器件包括将N位输入总线耦合到K位第一中间总线的压缩逻辑。第二组逻辑器件包括将K位第一中间总线和K位特征总线连接到K位第二中间总线的可交换算术操作逻辑。存储器存储设备包括将K位第二中间总线耦合到K位签名总线的存储元件。 K位特征总线也连接到有效数据输入信号路径。

4. 发明申请

WO2019190682A1 SYSTEM, APPARATUS AND METHOD FOR HANDSHAKING PROTOCOL FOR LOW POWER STATE TRANSITIONS 审中-公开
公开(公告)号：WO2019190682A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/019932
申请日：2019-02-28
申请人： INTEL CORPORATION
发明人： PAPPU, Lakshminarayana , MILSTREY, Robert , SRIVASTAVA, Amit Kumar
IPC分类号： G06F1/32 , G06F13/16 , G06F13/42 , G06F13/40
摘要： In one embodiment, an apparatus includes: at least one processing circuit; at least one array associated with the at least one processing circuit; a power controller to manage power consumption of the apparatus; and a fabric bridge coupled to the power controller. The fabric bridge and power controller may be configured to implement a handshaking protocol to enable the fabric bridge to receive data from the at least one array via a sideband communication path and send the data to a system memory coupled to the apparatus via a primary communication path, prior to entry of the apparatus into a first low power state. Other embodiments are described and claimed.

5. 发明申请

WO2017172308A1 APPARATUS AND METHOD FOR A SCALABLE TEST ENGINE 审中-公开
标题翻译：用于可扩展测试引擎的装置和方法
公开(公告)号：WO2017172308A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/021274
申请日：2017-03-08
申请人： INTEL CORPORATION
发明人： PAPPU, Lakshminarayana , DE GRUIJL, Robert , BHATT, Suketu U. , ADLER, Robert P. , GOPAL, Selvakumar Raja R. , TANADI, Rius
IPC分类号： G06F11/263 , G06F11/273
CPC分类号： G06F11/2736 , G01R31/31915 , G06F17/5045 , G06F2217/14 , G06F2217/66
摘要： An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.
摘要翻译：描述用于可扩展测试代理的设备和方法。例如，可伸缩测试引擎的一个实施例包括：输入接口，用于从处理器核心或外部测试系统接收命令和/或数据，所述命令和/或数据用于指定要在一个或多个测试操作上执行的一个或多个测试操作或更多芯片的知识产权（IP）块; 第一电路，用于通过互连结构建立与IP块的通信，所述第一电路响应于所接收的命令和/或数据将所述一个或多个测试操作发送到所述IP块，所述IP块用于处理所述测试操作并生成结果; 以及第二电路，用于通过互连结构从IP模块接收结果，结果从第二电路提供给处理器核心和/或外部测试系统用于分析。

6. 发明申请

WO2020190803A1 MEMORY CONTROLLER MANAGEMENT TECHNIQUES 审中-公开
公开(公告)号：WO2020190803A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022841
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： APPU, Abhishek R. , ANANTARAMAN, Aravindh , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , KOKER, Altug , MACPHERSON, Mike , MAIYURAN, Subramaniam , RAY, Joydeep , PAPPU, Lakshminarayana , GARCIA, Guadalupe
IPC分类号： G06F12/02 , G06F12/0804 , G06F12/0862 , G06F12/0893 , G06F9/38 , G06F15/173 , G06F12/12 , G06F12/128
摘要： Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.

7. 发明申请

WO2017151223A1 LOW COST INBUILT DETERMINISTIC TESTER FOR SOC TESTING 审中-公开
标题翻译：用于SOC测试的低成本INBUILT确定性测试仪
公开(公告)号：WO2017151223A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/012857
申请日：2017-01-10
申请人： INTEL CORPORATION
发明人： PAPPU, Lakshminarayana , CALLAHAN, Timothy J. , LEVY, Tomer
IPC分类号： G06F12/02 , G06F11/22
摘要： A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.
摘要翻译：用于高质量保证的高速芯片测试的方法和系统
。芯片上的多核系统具有多个处理核心。核心充当交易代理，在芯片边界上制造自动响应单元，自动响应单元基于接收到的读取请求的逻辑地址提供确定性返回值。

8. 发明公开

EP4453742A1 SYSTEM, METHOD, APPARATUS AND ARCHITECTURE FOR DYNAMICALLY CONFIGURING DEVICE FABRICS 失效
公开(公告)号：EP4453742A1
公开(公告)日：2024-10-30
申请号：EP22912221.3
申请日：2022-11-02
申请人： Intel Corporation
发明人： PAPPU, Lakshminarayana , HARRIMAN, David J. , NAGARAJAN, Ramadass , NATU, Mahesh S.
IPC分类号： G06F13/42
CPC分类号： G06F13/4221 , Y02D10/00

9. 发明公开

EP4270201A2 MEMORY CONTROLLER MANAGEMENT TECHNIQUES 审中-实审
公开(公告)号：EP4270201A2
公开(公告)日：2023-11-01
申请号：EP23197619.2
申请日：2020-03-14
申请人： INTEL Corporation
发明人： APPU, Abhishek R , ANANTARAMAN, Aravindh , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , KOKER, Altug , MACPHERSON, Mike , MAIYURAN, Subramaniam , RAY, Joydeep , PAPPU, Lakshminarayana , GARCIA, Guadalupe
IPC分类号： G06F12/06
摘要： Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.

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