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1. 发明申请

WO2017091254A1 CHANGING THE CLOCK FREQUENCY OF A COMPUTING DEVICE 审中-公开
标题翻译：改变计算设备的时钟频率
公开(公告)号：WO2017091254A1
公开(公告)日：2017-06-01
申请号：PCT/US2016/046871
申请日：2016-08-12
申请人： INTEL CORPORATION
发明人： GENDLER, Alexander , KNOLL, Ernest , NATHAN, Ofer , MISHAELI, Michael , SISTLA, Krishnakanth V. , SABBA, Ariel , REHANA, Shani , SZAPIRO, Ariel , KURTS, Tsvika , LEVY, Ofer
IPC分类号： G06F1/08 , H03L7/095 , G06F5/06
CPC分类号： H04L7/0331 , G06F1/08 , G06F1/10 , G06F1/324 , H04L7/0025 , H04L7/005 , Y02D10/126
摘要： Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
摘要翻译：描述了用于启用快速时钟频率转换的技术。计算设备的示例包括包含核心和非核心组件的中央处理单元（CPU）。计算设备还包括处理核心与非核心组件之间的数据事务的双模式FIFO。计算设备还包括频率控制单元，其可以指示核心转换到新的时钟频率。在转换到新时钟频率期间，双模式FIFO将继续处理核心与非核心组件之间的数据事务。

2. 发明申请

WO2009158247A2 POWER AWARE RETIREMENT 审中-公开
标题翻译：功率损失
公开(公告)号：WO2009158247A2
公开(公告)日：2009-12-30
申请号：PCT/US2009/047613
申请日：2009-06-17
申请人： INTEL CORPORATION , SPERBER, Zeev , MAROM, Rafi , LEVY, Ofer
发明人： SPERBER, Zeev , MAROM, Rafi , LEVY, Ofer
IPC分类号： G06F9/44 , G06F9/30 , G06F1/26 , G06F13/14
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/3855 , G06F9/3857 , G06F9/3865 , Y02D10/124 , Y02D10/171 , Y02D50/20
摘要： In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated with an executed instruction if information associated with the executed instruction is stored in an on-demand portion of at least one of arrays. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于接收和退出执行的指令的退休单元。退休单元可以包括用于在分配时接收信息的第一阵列和用于在执行之后接收信息的第二阵列。如果与所执行的指令相关联的信息被存储在阵列中的至少一个的按需部分中，退休单元还可以包括用于计算与执行的指令相关联的事件的逻辑。描述和要求保护其他实施例。

3. 发明申请

WO2014209312A1 TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 审中-公开
标题翻译：指令跟踪系统中处理设备的跟踪模式
公开(公告)号：WO2014209312A1
公开(公告)日：2014-12-31
申请号：PCT/US2013/048089
申请日：2013-06-27
申请人： INTEL CORPORATION , SCHMITT, Thilo , LACHNER, Peter , STRONG, Beeman , LEVY, Ofer , TOLL, Thomas , MERTEN, Matthew , LI, Tong , RAJWAR, Ravi , LAI, Konrad
发明人： SCHMITT, Thilo , LACHNER, Peter , STRONG, Beeman , LEVY, Ofer , TOLL, Thomas , MERTEN, Matthew , LI, Tong , RAJWAR, Ravi , LAI, Konrad
IPC分类号： G06F11/34 , G06F11/36
CPC分类号： G06F9/30189 , G06F11/3636
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.
摘要翻译：根据本文公开的实施例，提供了用于跟踪指令跟踪系统中的处理设备的模式的系统和方法。该方法可以包括接收处理设备的当前执行模式中的改变的指示。该方法还可以包括确定接收到的指示的当前执行模式不同于IT模块先前生成的第一执行模式（EM）分组的执行模式的值。该方法还可以包括基于确定当前执行模式不同而生成第二EM分组，其提供处理设备的当前执行模式的值以指示用于跟踪中的指令的执行模式的改变由IT模块生成。该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

4. 发明申请

WO2013101100A1 CAUSING AN INTERRUPT BASED ON EVENT COUNT 审中-公开
标题翻译：导致基于事件计数的中断
公开(公告)号：WO2013101100A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067914
申请日：2011-12-29
申请人： INTEL CORPORATION , YASIN, Ahmad , IRELAN, Peggy J. , LEVY, Ofer , ZIEDAN, Emile , ZHOU, Grant
发明人： YASIN, Ahmad , IRELAN, Peggy J. , LEVY, Ofer , ZIEDAN, Emile , ZHOU, Grant
IPC分类号： G06F13/14 , G06F13/24 , G06F9/30
CPC分类号： G06F9/3861 , G06F11/3466 , G06F11/3476 , G06F2201/86 , G06F2201/88
摘要： Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.
摘要翻译：一些实现提供了响应于多个事件的发生而在处理器中引起中断的技术和布置。第一事件计数器对处理器内事件类型的发生进行计数，并响应于达到第一预定义计数而输出信号以激活第二事件计数器。第二事件计数器对处理器内的事件类型的发生进行计数，并响应于达到第二预定义计数而导致处理器的中断。

5. 发明申请

WO2014105168A1 REAL TIME INSTRUCTION TRACE PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译：实时跟踪处理器，方法和系统
公开(公告)号：WO2014105168A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047431
申请日：2013-06-24
申请人： INTEL CORPORATION
发明人： KURTS, Tsvika , LEVY, Ofer , KAZACHINSKY, Itamar , MALKA, Gabi , SPERBER, Zeev , BRANDT, Jason W.
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
摘要翻译：一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。还公开了其它方法，装置和系统。

6. 发明申请

WO2013180738A1 SCATTER USING INDEX ARRAY AND FINITE STATE MACHINE 审中-公开
标题翻译：散射器使用索引阵列和有限状态机
公开(公告)号：WO2013180738A1
公开(公告)日：2013-12-05
申请号：PCT/US2012/040628
申请日：2012-06-02
申请人： INTEL CORPORATION , SPERBER, Zeev , VALENTINE, Robert , RAIKEN, Shlomo , SHWARTSMAN, Stanislav , OFIR, Gal , YANOVER, Igor , PATKIN, Guy , LEVY, Ofer
发明人： SPERBER, Zeev , VALENTINE, Robert , RAIKEN, Shlomo , SHWARTSMAN, Stanislav , OFIR, Gal , YANOVER, Igor , PATKIN, Guy , LEVY, Ofer
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305
CPC分类号： G06F15/7839 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3808 , G06F9/383
摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
摘要翻译：公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。设备的实施例可以包括：解码逻辑以解码散射/收集指令并产生微操作。索引数组保存一组索引和一组对应的掩码元素。有限状态机有助于散射操作。地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。正在生成的每组地址的缓冲区中分配存储空间。与生成的地址集相对应的数据元素被复制到缓冲器。如果对应的掩码元素具有所述第一值并且掩模元素被响应于它们各自的存储的完成而被改变为第二值，则访问该集合的地址以存储数据元素。

7. 发明申请

WO2018004959A1 METHOD AND LOGIC FOR MAINTAINING PERFORMANCE COUNTERS WITH DYNAMIC FREQUENCIES 审中-公开
标题翻译：用动态频率维护性能计数器的方法和逻辑
公开(公告)号：WO2018004959A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035257
申请日：2017-05-31
申请人： INTEL CORPORATION
发明人： YASIN, Ahmad , PARDO-FRIDMAN, Eti , LEVY, Ofer
IPC分类号： G06F9/30
摘要： A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.
摘要翻译：处理器包括前端和后端，前端包括用于解码来自指令流的指令的电路以及包括用于处理该指令的电路的核心。内核包括执行流水线，动态核心频率逻辑单元和计数器补偿逻辑单元。执行流水线包括执行指令的电路。动态核心频率逻辑单元包括压缩核心的时钟以降低核心频率的电路。时钟可能对软件不可见。计数器补偿逻辑单元包括用于基于至少动态核心频率逻辑单元电路来调整与性能计数器相关联的性能计数器增量以调整核心的时钟以降低核心频率的电路。

8. 发明授权

EP3014452B1 TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 有权转让
公开(公告)号：EP3014452B1
公开(公告)日：2019-06-05
申请号：EP13887960.6
申请日：2013-06-27
申请人： Intel Corporation
发明人： SCHMITT, Thilo , LACHNER, Peter , STRONG, Beeman , LEVY, Ofer , TOLL, Thomas , MERTEN, Matthew , LI, Tong , RAJWAR, Ravi , LAI, Konrad
IPC分类号： G06F11/36 , G06F9/30

9. 发明公开

EP3014452A1 TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 有权转让
标题翻译： CHASE模式的处理设备，以便跟踪系统
公开(公告)号：EP3014452A1
公开(公告)日：2016-05-04
申请号：EP13887960.6
申请日：2013-06-27
申请人： Intel Corporation
发明人： SCHMITT, Thilo , LACHNER, Peter , STRONG, Beeman , LEVY, Ofer , TOLL, Thomas , MERTEN, Matthew , LI, Tong , RAJWAR, Ravi , LAI, Konrad
IPC分类号： G06F11/34 , G06F11/36
CPC分类号： G06F9/30189 , G06F11/3636
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

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