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1. 发明申请

WO2015147792A1 INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES 审中-公开
标题翻译：用于制造纳米器件的内部间隔件的集成方法
公开(公告)号：WO2015147792A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/031632
申请日：2014-03-24
申请人： INTEL CORPORATION
发明人： KIM, Seiyon , SIMON, Daniel A. , KUHN, Kelin J. , WARD, Curtis W.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/764
CPC分类号： H01L29/66553 , B82Y10/00 , H01L21/764 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/775 , H01L29/78618 , H01L29/78696
摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.
摘要翻译：公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。在一个实施例中，通过在与沟道区相邻蚀刻的凹坑中沉积光可定义的间隔物材料来形成内部间隔物。通过改变凹坑之外的材料的蚀刻特性并且选择性地去除在凹坑之外的改变的光可定义材料，可光限定的材料保留在凹坑中。

2. 发明申请

WO2013095650A1 NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：具有非离散源和排水区的纳米结构
公开(公告)号：WO2013095650A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067232
申请日：2011-12-23
申请人： INTEL CORPORATION , CEA, Stephen M. , CAPPELLANI, Annalisa , GILES, Martin D. , RIOS, Rafael , KIM, Seiyon , KUHN, Kelin J.
发明人： CEA, Stephen M. , CAPPELLANI, Annalisa , GILES, Martin D. , RIOS, Rafael , KIM, Seiyon , KUHN, Kelin J.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78618 , B82Y40/00 , H01L21/268 , H01L29/0673 , H01L29/0847 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66742 , H01L29/66787 , H01L29/66977 , H01L29/7839 , H01L29/7845 , H01L29/7848 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
摘要翻译：描述了具有非离散源极和漏极区域的纳米线结构。例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。每个纳米线包括设置在纳米线中的离散通道区域。栅电极堆叠围绕多个垂直堆叠的纳米线。一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

3. 发明申请

WO2016048377A1 METAL OXIDE METAL FIELD EFFECT TRANSISTORS (MOMFETS) 审中-公开
标题翻译：金属氧化物金属场效应晶体管（MOMFETS）
公开(公告)号：WO2016048377A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057867
申请日：2014-09-26
申请人： INTEL CORPORATION
发明人： RIOS, Rafael , KUHN, Kelin J. , KIM, Seiyon , WEBER, Justin R.
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/66439 , H01L21/84 , H01L27/1203 , H01L29/0669 , H01L29/0673 , H01L29/122 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/42356 , H01L29/42364 , H01L29/4238 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/775 , H01L29/778 , H01L29/78636 , H01L29/78681 , H01L29/78684 , H01L29/78696 , H01L49/00
摘要： Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an N-type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.
摘要翻译：本发明的实施例包括金属氧化物金属场效应晶体管（MOMFET）以及制造这种器件的方法。在实施例中，MOMFET器件包括源极和漏极，沟道设置在源极和漏极之间。根据实施例，通道具有在通道中产生量子限制效应的至少一个约束尺寸。在一个实施例中，MOMFET器件还包括通过栅极电介质与沟道分离的栅电极。根据实施例，可以通过改变通道的尺寸，用于通道的材料和/或施加到通道的表面终端来调制通道的带隙能量。实施例还包括通过相对于通道的导频带和能带能量控制源极和漏极的功函数来形成N型器件和P型器件。

4. 发明申请

WO2015199721A1 MAGNETIC NANOMECHANICAL DEVICES FOR STICTION COMPENSATION 审中-公开
标题翻译：用于补偿的磁性纳米器件
公开(公告)号：WO2015199721A1
公开(公告)日：2015-12-30
申请号：PCT/US2014/044594
申请日：2014-06-27
申请人： INTEL CORPORATION
发明人： MUNOZ, Jorge A. , NIKONOV, Dmitri E. , KUHN, Kelin J. , THEOFANIS, Patrick , PAWASHE, Chytra , LIN, Kevin , KIM, Seiyon
IPC分类号： B81B7/02
CPC分类号： B82B1/005 , B81B3/0016 , B81B7/02 , B81B2201/014 , B81B2203/0118 , B82B1/002 , B82B3/0023 , B82Y15/00 , B82Y25/00 , B82Y40/00 , H01H1/0094 , H01H1/54 , H01H59/0009 , H01L29/66227 , H01L29/82 , H01L29/84 , Y10S977/732 , Y10S977/838 , Y10S977/888 , Y10S977/938
摘要： Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.
摘要翻译：描述了具有改进的工作电压范围的纳米磁体和改进的悬臂尺寸控制的纳米机电（NEMS）装置。例如，在一个实施例中，纳米机电（NEMS）器件包括衬底层，设置在衬底层上方的第一磁性层，设置在第一磁性层上方的第一介电层，设置在第一介电层上方的第二电介质，以及布置在第二介电层上方的悬臂。当向悬臂施加电压时，悬臂从第一位置弯曲到第二位置朝向衬底层。

5. 发明申请

WO2013154574A1 CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR 审中-公开
标题翻译：应变诱导缓冲器对电绝缘子的转换
公开(公告)号：WO2013154574A1
公开(公告)日：2013-10-17
申请号：PCT/US2012/033472
申请日：2012-04-13
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , LE, Van H. , GLASS, Glenn A. , KUHN, Kelin J. , CEA, Stephen M.
发明人： CAPPELLANI, Annalisa , LE, Van H. , GLASS, Glenn A. , KUHN, Kelin J. , CEA, Stephen M.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02236 , H01L21/02238 , H01L21/02241 , H01L21/02255 , H01L21/02304 , H01L21/02439 , H01L21/0245 , H01L21/02455 , H01L21/02488 , H01L21/02532 , H01L21/306 , H01L21/76 , H01L21/7624 , H01L21/76283 , H01L29/0603 , H01L29/0642 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/7378 , H01L29/785 , H01L33/12 , H05K1/18
摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
摘要翻译：公开了用于将应变诱导半导体缓冲层转变成缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括从生长出来的那些在应变诱导缓冲器上并具有埋入的电绝缘体层。例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

6. 发明申请

WO2013095443A1 SEMICONDUCTOR DEVICES HAVING THREE-DIMENSIONAL BODIES WITH MODULATED HEIGHTS 审中-公开
标题翻译：具有调制高度的三维体的半导体器件
公开(公告)号：WO2013095443A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066544
申请日：2011-12-21
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , DAVILA, Aura , GHANI, Tahir
发明人： CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , DAVILA, Aura , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7831 , H01L21/3083 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66484
摘要： Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different.
摘要翻译：描述具有调制高度的三维体的半导体器件和形成这种器件的方法。例如，半导体结构包括具有设置在基板上方的第一半导体本体的第一半导体器件。第一半导体本体具有第一高度和具有第一水平面的最上表面。半导体结构还包括具有设置在衬底上方的第二半导体本体的第二半导体器件。第二半导体本体具有第二高度和具有第二水平面的最上表面。第一和第二水平面是共面的，第一和第二高度是不同的。

7. 发明申请

WO2014004049A1 ISOLATED AND BULK SEMICONDUCTOR DEVICES FORMED ON A SAME BULK SUBSTRATE 审中-公开
标题翻译：在相同的大块基板上形成的隔离和大块半导体器件
公开(公告)号：WO2014004049A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/044794
申请日：2013-06-07
申请人： INTEL CORPORATION
发明人： CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , GOMEZ, Harry
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76237 , H01L21/76232 , H01L27/088 , H01L27/1207 , H01L29/0638 , H01L29/0653 , H01L29/7851
摘要： Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
摘要翻译：描述了形成在相同体积基板上的隔离和体半导体器件以及形成这种器件的方法。例如，半导体结构包括具有设置在体基板上的第一半导体本体的第一半导体器件。第一半导体本体具有带有第一水平面的最上表面。半导体结构还包括具有设置在隔离基座上的第二半导体本体的第二半导体器件。隔离基座设置在主体基板上。第二半导体本体具有带有第二水平面的最上表面。第一和第二水平面是共面的。

8. 发明申请

WO2013095645A1 SEMICONDUCTOR DEVICES HAVING MODULATED NANOWIRE COUNTS 审中-公开
标题翻译：具有调制纳米级数的半导体器件
公开(公告)号：WO2013095645A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067223
申请日：2011-12-23
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , BHIMARASETTI, Gopinath , GHANI, Tahir , KIM, Seiyon
发明人： CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , BHIMARASETTI, Gopinath , GHANI, Tahir , KIM, Seiyon
IPC分类号： H01L21/336 , H01L29/78 , B82B3/00
CPC分类号： H01L27/0886 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02587 , H01L29/0673 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
摘要翻译：描述了具有调制纳米线计数的半导体器件和形成这种器件的方法。例如，半导体结构包括具有多个纳米线的第一半导体器件，该多个纳米线设置在衬底上并且堆叠在具有第一最上层纳米线的第一垂直平面中。第二半导体器件具有设置在衬底上方的一个或多个纳米线并且堆叠在具有第二最上层纳米线的第二垂直平面中。第二半导体器件包括比第一半导体器件少的一个或多个纳米线。第一和第二最上层的纳米线设置在与第一和第二垂直平面正交的同一平面中。

9. 发明申请

WO2012074872A2 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 审中-公开
标题翻译：硅和硅纳米线的纳米结构
公开(公告)号：WO2012074872A2
公开(公告)日：2012-06-07
申请号：PCT/US2011/062059
申请日：2011-11-23
申请人： INTEL CORPORATION , KUHN, Kelin J. , KIM, Seiyon , RIOS, Rafael , CEA, Stephen M. , GILES, Martin D. , CAPPELLANI, Annalisa , RAKSHIT, Titash , CHANG, Peter , RACHMADY, Willy
发明人： KUHN, Kelin J. , KIM, Seiyon , RIOS, Rafael , CEA, Stephen M. , GILES, Martin D. , CAPPELLANI, Annalisa , RAKSHIT, Titash , CHANG, Peter , RACHMADY, Willy
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述了形成微电子结构的方法。那些方法的实施例包括形成包括衬底的纳米线器件，所述衬底包括与间隔物相邻的源极/漏极结构以及设置在间隔物之间的纳米线沟道结构，其中纳米线沟道结构垂直堆叠在彼此之上。

10. 发明申请

WO2012040075A2 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有单向应变鳍的非平面装置及其制造方法
公开(公告)号：WO2012040075A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/052084
申请日：2011-09-19
申请人： INTEL CORPORATION , CEA, Stephen M. , KOTLYAR, Roza , KAVALIEROS, Jack T. , GILES, Martin D. , GHANI, Tahir , KUHN, Kelin J. , KUHN, Markus , ZELICK, Nancy M.
发明人： CEA, Stephen M. , KOTLYAR, Roza , KAVALIEROS, Jack T. , GILES, Martin D. , GHANI, Tahir , KUHN, Kelin J. , KUHN, Markus , ZELICK, Nancy M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
摘要翻译：根据该方法制造的方法和装置。该方法包括：提供包括第一材料的衬底;以及提供包括第二材料的鳍片，鳍片设置在衬底上并且具有器件有源部分，第一材料和第二材料在其各自的晶体结构之间呈现晶格失配。提供鳍片包括：在衬底上提供包括第二材料的双轴应变膜; 并去除部分双轴应变薄膜，从而形成基本上单轴应变的翅片。

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