专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10114643B2 Techniques for detecting return-oriented programming 有权
公开(公告)号：US10114643B2
公开(公告)日：2018-10-30
申请号：US14129531
申请日：2013-05-23
申请人： INTEL CORPORATION
发明人： Koichi Yamada , Palanivelra Shanmugavelayutham , Arvind Krishnaswamy , Jason M. Agron , Jiwei Lu
IPC分类号： G06F9/30 , G06F21/54 , G06F12/08 , G06F12/0875
摘要： Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

2. 发明授权

US09411363B2 Synchronization in a computing device 有权
标题翻译：计算设备中的同步
公开(公告)号：US09411363B2
公开(公告)日：2016-08-09
申请号：US14565512
申请日：2014-12-10
申请人： Intel Corporation
发明人： Keqiang Wu , Jiwei Lu , Yong-Fong Lee
IPC分类号： G06F9/46 , G06F1/12 , G06F9/30
CPC分类号： G06F9/30065 , G06F8/52 , G06F8/70 , G06F9/30087 , G06F11/3024 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/825 , G06F2201/865 , G06F2201/88
摘要： One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.
摘要翻译：一个实施例提供了一种装置。该装置包括处理器，芯片组，用于存储处理的存储器和逻辑。处理器包括一个或多个核心，并且是执行该过程。逻辑是响应于大于检测利用阈值（UT）的平台处理器利用参数（PUP）来获取性能监视数据，至少部分地基于检测到的热功能和 /或检测到的热循环，使用二进制转换修改所识别的自旋循环，以创建经修改的处理部分，并且实现从所识别的旋转循环到修改的处理部分的重定向。

3. 发明授权

US09477453B1 Technologies for shadow stack manipulation for binary translation systems 有权
标题翻译：二进制翻译系统的影子栈操作技术
公开(公告)号：US09477453B1
公开(公告)日：2016-10-25
申请号：US14748363
申请日：2015-06-24
申请人： Intel Corporation
发明人： Tugrul Ince , Koichi Yamada , Paul Caprioli , Jiwei Lu
IPC分类号： G06F9/45 , G06F12/08
CPC分类号： G06F8/52 , G06F9/4486 , G06F12/08 , G06F2212/451
摘要： Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.
摘要翻译：用于阴影堆栈管理的技术包括计算设备，当在翻译的二进制文件中执行转换的调用例程时，将本地返回地址推送到计算设备的本机堆栈，向计算设备的堆栈指针添加恒定偏移量，对转换后的呼叫目标执行本机调用指令，执行本地调用指令后，从堆栈指针中减去常量偏移量。执行本地调用指令将转换后的返回地址推送到计算设备的影子栈上。计算设备可以将阴影栈的两个或多个虚拟存储器页面映射到单个物理存储器页面上。计算设备可以执行翻译的返回例程，其从本机堆栈弹出本地返回地址，将常量偏移量添加到堆栈指针，并执行本地返回指令。描述和要求保护其他实施例。

4. 发明申请

US20160170438A1 SYNCHRONIZATION IN A COMPUTING DEVICE 有权
标题翻译：计算设备中的同步
公开(公告)号：US20160170438A1
公开(公告)日：2016-06-16
申请号：US14565512
申请日：2014-12-10
申请人： Intel Corporation
发明人： Keqiang WU , Jiwei Lu , Yong-Fong Lee
IPC分类号： G06F1/12 , G06F9/30
CPC分类号： G06F9/30065 , G06F8/52 , G06F8/70 , G06F9/30087 , G06F11/3024 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/825 , G06F2201/865 , G06F2201/88
摘要： One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.
摘要翻译：一个实施例提供了一种装置。该装置包括处理器，芯片组，用于存储处理的存储器和逻辑。处理器包括一个或多个核心，并且是执行该过程。逻辑是响应于大于检测利用阈值（UT）的平台处理器利用参数（PUP）来获取性能监视数据，至少部分地基于检测到的热功能和 /或检测到的热循环，使用二进制转换修改所识别的自旋循环，以创建经修改的处理部分，并且实现从所识别的旋转循环到修改的处理部分的重定向。

5. 发明授权

US10642644B2 Memory management method and apparatus 有权
公开(公告)号：US10642644B2
公开(公告)日：2020-05-05
申请号：US15193562
申请日：2016-06-27
申请人： Intel Corporation
发明人： Keqiang Wu , Jiwei Lu , Koichi Yamada , Yong-Fong Lee
IPC分类号： G06F9/46
CPC分类号： G06F9/467
摘要： Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

6. 发明授权

US09990233B2 Binary translation for multi-processor and multi-core platforms 有权
公开(公告)号：US09990233B2
公开(公告)日：2018-06-05
申请号：US14129420
申请日：2013-06-28
申请人： Intel Corporation
发明人： Abhik Sarkar , Jiwei Lu , Palanivelrajan Rajan Shanmugavelayutham , Jason M. Agron , Koichi Yamada
IPC分类号： G06F9/445 , G06F9/455 , G06F9/48 , G06F9/50 , G06F12/02 , G06F12/0802
CPC分类号： G06F9/5038 , G06F8/61 , G06F8/62 , G06F9/45516 , G06F9/485 , G06F9/5016 , G06F12/0253 , G06F12/0802 , G06F2212/1044 , G06F2212/60
摘要： Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.

7. 发明授权

US11507412B2 Memory management method and apparatus 有权
公开(公告)号：US11507412B2
公开(公告)日：2022-11-22
申请号：US16861082
申请日：2020-04-28
申请人： Intel Corporation
发明人： Keqiang Wu , Jiwei Lu , Koichi Yamada , Yong-Fong Lee
IPC分类号： G06F9/46
摘要： A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

8. 发明授权

US10789056B2 Technologies for scalable translation caching for binary translation systems 有权
公开(公告)号：US10789056B2
公开(公告)日：2020-09-29
申请号：US15202745
申请日：2016-07-06
申请人： Intel Corporation
发明人： Koichi Yamada , Jose A. Baiocchi Paredes , Abhik Sarkar , Ajay Harikumar , Jiwei Lu
IPC分类号： G06F8/52 , G06F8/61
摘要： Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式