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1. 发明申请

WO2017111770A1 TRANSISTOR WITH DUAL-GATE SPACER 审中-公开
标题翻译：双栅隔离晶体管
公开(公告)号：WO2017111770A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000170
申请日：2015-12-23
申请人： INTEL CORPORATION
发明人： LIU, En-shao , PARK, Joodong , LEE, Chen-guan , JAN, Chia-hong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/0649 , H01L29/0673 , H01L29/401 , H01L29/42372 , H01L29/775
摘要： Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a "T" shape or various derivatives of that shape such as 1-shape or Γ-shape, for example.
摘要翻译：公开了用于形成具有一个或多个附加栅极间隔物的晶体管的技术。例如，可以在栅极栅极间隔物和原始栅极间隔物之间形成额外的间隔物，以减少栅极与源极/漏极之间的寄生耦合。在一些情况下，附加间隔物可以包括气隙和/或电介质材料（例如，低k电介质材料）。在一些情况下，闸门可以包括下部和上部。在一些这样的情况下，栅极的下部分在原始栅极间隔物之间的宽度可以比栅极的上部分更窄，这可能是由于额外的间隔物位于栅极的下部分和原始的栅栏垫片。在一些这样的情况下，门可以近似于“T” 形状或该形状的各种衍生物，例如1形或Γ形。

2. 发明申请

WO2018111226A1 TRANSISTOR WITH ASYMMETRIC THRESHOLD VOLTAGE CHANNEL 审中-公开
公开(公告)号：WO2018111226A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066232
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： LEE, Chen-guan , CHANG, Hsu-yu , PARK, Joodong , HAFEZ, Walid M. , JAN, Chia-hong
IPC分类号： H01L29/78 , H01L29/66
摘要： Embodiments herein describe techniques for a transistor including a drain, a source, and a channel between the drain and the source. The channel may include a first channel portion and a second channel portion adjacent to the first channel portion. The transistor may include a gate, wherein the gate may include a first gate portion and a second gate portion, where the first gate portion may include a first metal, and the second gate portion may include a second metal different from the first metal. The first gate portion may overlap the first channel portion, and the first gate portion and the second gate portion may overlap the second channel portion.

3. 发明申请

WO2008005377A3 SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE 审中-公开
公开(公告)号：WO2008005377A3
公开(公告)日：2008-01-10
申请号：PCT/US2007/015224
申请日：2007-06-28
申请人： INTEL CORPORATION , CURELLO, Giuseppe , POST, Ian, R. , JAN, Chia-hong , BOHR, Mark
发明人： CURELLO, Giuseppe , POST, Ian, R. , JAN, Chia-hong , BOHR, Mark
IPC分类号： H01L21/336 , H01L29/78
摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

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