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1. 发明申请

WO2006039183A3 EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES 审中-公开
公开(公告)号：WO2006039183A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/034010
申请日：2005-09-21
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
发明人： WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
IPC分类号： G06F9/32
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

2. 发明申请

WO2017052989A1 TECHNOLOGIES FOR OFFLOADING DATA OBJECT REPLICATION AND SERVICE FUNCTION CHAIN MANAGEMENT 审中-公开
标题翻译：用于卸载数据对象复制和服务功能链管理的技术
公开(公告)号：WO2017052989A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048847
申请日：2016-08-26
申请人： INTEL CORPORATION
发明人： KUMAR, Dinesh , JANI, Nrupal R , WANG, Ren , MACIOCCO, Christian , JAIN, Sanjeev
IPC分类号： H04L29/08
CPC分类号： H04L67/2804 , H04L45/306 , H04L47/26 , H04L49/70 , H04L67/10 , H04L67/1095 , H04L67/1097
摘要： Technologies for offloading data object replication and service function chain management include a switch communicatively coupled to one or more computing nodes capable of executing virtual machines and storing data objects. The switch is configured to determine metadata of a service function chain, transmit a network packet to a service function of the service function chain being executed by one or more of the computing nodes for processing the network packet. The switch is further configured to receive feedback from service function, update the metadata based on the feedback, and transmit the network packet to a next service function of the service function chain. Additionally or alternatively, the switch is configured to identify a plurality of computing nodes (i.e., storage nodes) at which to store a received data object, replicate the data object based on the number of storage nodes, and transmit each of the received data object and replicated data object(s) to different corresponding storage nodes. Other embodiments are described and claimed.
摘要翻译：用于卸载数据对象复制和服务功能链管理的技术包括通信地耦合到能够执行虚拟机并存储数据对象的一个或多个计算节点的交换机。交换机被配置为确定服务功能链的元数据，将网络分组传送到由一个或多个计算节点执行的服务功能链的服务功能，以处理网络分组。交换机还被配置为从服务功能接收反馈，基于反馈更新元数据，并将网络分组发送到服务功能链的下一个服务功能。附加地或替代地，交换机被配置为识别在其上存储接收到的数据对象的多个计算节点（即，存储节点），基于存储节点的数量来复制数据对象，并且发送每个接收到的数据对象并将数据对象复制到不同的对应存储节点。描述和要求保护其他实施例。

3. 发明申请

WO2016209587A1 APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING 审中-公开
标题翻译：用于硬件加速分组处理的装置和方法
公开(公告)号：WO2016209587A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/035518
申请日：2016-06-02
申请人： INTEL CORPORATION
发明人： JANI, Nrupal , KUMAR, Dinesh , MACIOCCO, Christian , WANG, Ren , PARIKH, Neerav , FASTABEND, John , GASPARAKIS, Iosif , HARRIMAN, David J. , CONNOR, Patrick L. , JAIN, Sanjeev
IPC分类号： G06F13/40 , H04L12/933 , H04L12/931
CPC分类号： H04L45/44 , H04L43/026 , H04L43/0817 , H04L43/0876 , H04L43/16 , H04L45/306 , H04L47/125 , H04L47/781
摘要： Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.
摘要翻译：本文描述了用于硬件加速分组处理的设备和技术。设备可以与一个或多个硬件交换机进行通信。该设备可以检测多个分组流的特性。该设备可以基于检测到的多个分组流的特性，在一个或多个硬件交换机和软件数据平面组件之间分配多个分组流，使得至少一个分组流被指定为被一个或多个硬件开关还描述了其它实施例。

4. 发明申请

WO2006074047A1 PROVIDING ACCESS TO DATA SHARED BY PACKET PROCESSING THREADS 审中-公开
标题翻译：提供对通过分组处理螺纹共享的数据的访问
公开(公告)号：WO2006074047A1
公开(公告)日：2006-07-13
申请号：PCT/US2005/047379
申请日：2005-12-23
申请人： INTEL CORPORATION , JAIN, Sanjeev , HOOPER, Donald, F.
发明人： JAIN, Sanjeev , HOOPER, Donald, F.
IPC分类号： G06F12/08 , H04L12/56
CPC分类号： G06F12/0815 , H04L47/50
摘要： In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.
摘要翻译：通常，一方面，本发明描述了一种方法，其包括在第一核心处执行的第一分组处理线程，对包括第一线程的分组处理线程之间共享的数据执行存储器读取。该方法还包括在第一分组处理线程中，在由第一分组处理线程执行对共享数据的排他操作之前，确定由存储器读取返回的数据是否被在另一核上操作的分组处理线程改变。

5. 发明申请

WO2017172183A1 PIPELINED HASH TABLE WITH REDUCED COLLISIONS 审中-公开
标题翻译：带有减少碰撞的管道式散列表
公开(公告)号：WO2017172183A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019931
申请日：2017-02-28
申请人： INTEL CORPORATION
发明人： JAIN, Sanjeev , PAPADANTONAKIS, Karl S. , SOUTHWORTH, Robert G. , GRAVEL, Alain , DAMA, Jonathan A.
IPC分类号： G06F12/1018
摘要： Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.
摘要翻译：本文描述了用于流水线散列的设备和方法。执行流水线散列函数的示例装置可以包括：第一存储器，用于存储第一多个桶记录;第二存储器，用于存储第二多个桶记录;以及散列电路，用于接收密钥并执行流水线散列函数使用密钥来提供散列值。散列电路还用于基于散列值的第一比特子集从第一存储器中选择第一多个桶记录中的第一桶记录。散列电路进一步基于第一桶记录的内容和散列值的第二比特子集来提供多个条目记录中的条目记录的特定条目的位置。

6. 发明申请

WO2006069355A2 METHOD AND APPARATUS TO PROVIDE EFFICIENT COMMUNICATION BETWEEN PROCESSING ELEMENTS IN A PROCESSOR UNIT 审中-公开
标题翻译：在处理器单元中处理元素之间提供有效通信的方法和装置
公开(公告)号：WO2006069355A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/046937
申请日：2005-12-20
申请人： INTEL CORPORATION , ROSENBLUTH, Mark , JAIN, Sanjeev , WOLRICH, Gilbert
发明人： ROSENBLUTH, Mark , JAIN, Sanjeev , WOLRICH, Gilbert
CPC分类号： G06F13/4252
摘要： A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.
摘要翻译：上下文转发总线在具有多个处理单元的处理器单元中有效地传送处理单元之间的控制和数据。控制和数据信息通过第一总线从处理元件传送到处理元件。

7. 发明申请

WO2006069126A2 METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK 审中-公开
标题翻译：用存储器块支持多个存储器银行的方法和设备
公开(公告)号：WO2006069126A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/046297
申请日：2005-12-20
申请人： INTEL CORPORATION , JAIN, Sanjeev , WOLRICH, Gilbert , ROSENBLUTH, Mark , BERNSTEIN, Debra
发明人： JAIN, Sanjeev , WOLRICH, Gilbert , ROSENBLUTH, Mark , BERNSTEIN, Debra
IPC分类号： G06F13/16
CPC分类号： G06F13/1673
摘要： A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.
摘要翻译：存储器控制器系统包括用于存储用于多个存储体的命令的存储器命令存储模块。该系统包括多个控制机构，每个控制机构包括第一和第二指针，以与每个模块位置中的下一个字段结合提供用于多个存储体中给定的一个存储体的命令的链接列表。 p>

8. 发明申请

WO2006063298A1 TECHNIQUES TO MANAGE FLOW CONTROL 审中-公开
标题翻译：管理流量控制技术
公开(公告)号：WO2006063298A1
公开(公告)日：2006-06-15
申请号：PCT/US2005/044750
申请日：2005-12-09
申请人： INTEL CORPORATION , JAIN, Sanjeev , ROSENBLUTH, Mark , WOLRICH, Gilbert , WILKINSON, Hugh
发明人： JAIN, Sanjeev , ROSENBLUTH, Mark , WOLRICH, Gilbert , WILKINSON, Hugh
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L49/15 , H04L49/254 , H04L49/30 , H04L2012/5678
摘要： A network device comprises an ingress processor (400) and an egress processor (450) connected via a flow control bus (485). Flow control messages received by a traffic manager module (489) comprised by the ingress processor are sent to a transmit path (498) and a control path (497).
摘要翻译：网络设备包括通过流量控制总线（485）连接的入口处理器（400）和出口处理器（450）。由入口处理器组成的流量管理器模块（489）接收的流量控制消息被发送到发送路径（498）和控制路径（497）。

9. 发明公开

EP3353997A1 TECHNOLOGIES FOR OFFLOADING DATA OBJECT REPLICATION AND SERVICE FUNCTION CHAIN MANAGEMENT 有权
公开(公告)号：EP3353997A1
公开(公告)日：2018-08-01
申请号：EP16849303.9
申请日：2016-08-26
申请人： Intel Corporation
发明人： KUMAR, Dinesh , JANI, Nrupal R , WANG, Ren , MACIOCCO, Christian , JAIN, Sanjeev
IPC分类号： H04L29/08
CPC分类号： H04L67/2804 , H04L45/306 , H04L47/26 , H04L49/70 , H04L67/10 , H04L67/1095 , H04L67/1097
摘要： Technologies for offloading data object replication and service function chain management include a switch communicatively coupled to one or more computing nodes capable of executing virtual machines and storing data objects. The switch is configured to determine metadata of a service function chain, transmit a network packet to a service function of the service function chain being executed by one or more of the computing nodes for processing the network packet. The switch is further configured to receive feedback from service function, update the metadata based on the feedback, and transmit the network packet to a next service function of the service function chain. Additionally or alternatively, the switch is configured to identify a plurality of computing nodes (i.e., storage nodes) at which to store a received data object, replicate the data object based on the number of storage nodes, and transmit each of the received data object and replicated data object(s) to different corresponding storage nodes. Other embodiments are described and claimed.

10. 发明公开

EP1807755A2 EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES 审中-公开
标题翻译：数据处理引擎代码区由相邻的控制程序的详细信息保存共享作为使用嵌套扩展
公开(公告)号：EP1807755A2
公开(公告)日：2007-07-18
申请号：EP05799874.2
申请日：2005-09-21
申请人： Intel Corporation
发明人： WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
IPC分类号： G06F9/32
CPC分类号： G06F12/0607 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

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