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1. 发明申请

WO2022115141A1 ENHANCED GRATING ALIGNED PATTERNING FOR EUV DIRECT PRINT PROCESSES 审中-公开
公开(公告)号：WO2022115141A1
公开(公告)日：2022-06-02
申请号：PCT/US2021/051379
申请日：2021-09-21
申请人： INTEL CORPORATION
发明人： M BARGHI, Seyedhamed , KADALI, Shyam Benegal , PAIK, Marvin Y. , FANG, Sheng-Po , GULER, Leonard P. , WALLACE, Charles H. , JEONG, James Y.
IPC分类号： H01L21/033 , H01L21/768 , H01L21/311
摘要： Embodiments disclosed herein include methods of patterning a back-end-of-line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.

2. 发明申请

WO2018063323A1 VIA & PLUG ARCHITECTURES FOR INTEGRATED CIRCUIT INTERCONNECTS & METHODS OF MANUFACTURE 审中-公开
标题翻译：用于集成电路互连和制造方法的威盛＆塞普结构
公开(公告)号：WO2018063323A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054770
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： GULER, Leonard P. , WALLACE, Charles H. , NYHUS, Paul A.
IPC分类号： H01L21/768
CPC分类号： H01L23/522 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L23/5226 , H01L23/5283 , H01L23/5329
摘要： Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.
摘要翻译：用于形成金属线插塞的方法和架构，所述金属线插塞限定两个金属线端之间的间隔，并且用于形成将金属线互连到下伏接触的通孔。线插头与金属线在平面上，而连接线的通孔在下面的平面中。以给定节距（P）打印线的一个平版印版或分划板可以多次使用，例如每次以节距对分（P / 2）或节距四分法（P / 4）构图技术来限定金属线末端和金属线过孔。一维（1D）光栅掩模可以与交叉光栅（正交）掩模结构一起使用，该结构同样适用于音调分离技术。

3. 发明申请

WO2017171715A1 PITCH DIVISION PATTERNING APPROACHES WITH INCREASED OVERLAY MARGIN FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
标题翻译： PITCH DIVISION PATTERNING方法增加覆盖面积（线条）的后端（BEOL）互连制造和结构造成的
公开(公告)号：WO2017171715A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/024553
申请日：2016-03-28
申请人： INTEL CORPORATION
发明人： WALLACE, Charles H. , GULER, Leonard P. , CHANDHOK, Manish , NYHUS, Paul A.
IPC分类号： H01L21/027 , H01L21/768 , H01L21/28
摘要： Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.
摘要翻译：描述了用于后端线路（BEOL）互连制造的增加的覆盖裕度和所得到的结构的节距分割图案化方法。在一个示例中，一种方法包括在形成在衬底上方的第一牺牲材料中形成第一多个导电线。第一多个导电线沿着BEOL金属化层的方向形成并且以间距间隔开。该方法还包括去除第一牺牲材料，形成与第一多个导电线的侧壁相邻的第二牺牲材料，然后形成与第二牺牲材料相邻的第二多个导电线。第二多个导电线沿着BEOL金属化层的方向形成，以间距间隔开，并且与第一多个导电线交替。该方法还包括去除第二牺牲层。

4. 发明申请

WO2018125212A1 FIN PATTERNING FOR SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：WO2018125212A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069501
申请日：2016-12-30
申请人： INTEL CORPORATION
发明人： BAYKAN, Mehmet O. , GULER, Leonard P. , JAIN, Anurag , FREEMAN, Gordon S. , BIGWOOD, Robert M.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/762
CPC分类号： H01L27/0924 , H01L21/762 , H01L21/823821 , H01L29/66
摘要： Embodiments herein describe techniques for forming multiple cut regions with orthogonal corners on multiple fins of a semiconductor device based on multiple masks formed by using sacrificial layers with embedded grating lines. A cut region with orthogonal corners on a fin may be formed based on a mask with the aid of the grating lines embedded within a sacrificial layer, where the irregular shape of the mask may land on the grating lines without affecting the cut region formed on the fin. Multiple cut regions formed by multiple masks may be accumulated on a sacrificial layer, which may act as an intermediate patterning layer. Multiple cut regions with orthogonal corners on multiple fins may be formed in a single pass based on the multiple cut regions accumulated on the intermediate patterning layer. Other embodiments may also be described and claimed.

5. 发明申请

WO2017105445A1 GRID SELF-ALIGNED METAL VIA PROCESSING SCHEMES FOR BACK END OF LINE (BEOL) INTERCONNECTS AND STRUCTURES RESULTING THEREFROM 审中-公开
标题翻译：网格自对准金属通过处理方案处理线路（BEOL）互连和结构的后端
公开(公告)号：WO2017105445A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/066172
申请日：2015-12-16
申请人： INTEL CORPORATION
发明人： GULER, Leonard P.
IPC分类号： H01L21/60 , H01L21/033
CPC分类号： H01L21/76834 , H01L21/76811 , H01L21/76816 , H01L21/76897 , H01L23/528 , H01L24/16 , H01L24/24 , H01L2224/16225 , H01L2224/24137 , H01L2924/00014 , H01L2924/14 , H01L2224/13099
摘要： Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate, the dielectric lines raised above the metal lines. A hardmask layer is formed on the metal lines of the lower metallization layer, between and co-planar with the dielectric lines of the lower metallization layer. A grating structure is formed above and orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. A mask is formed above the grating structure. Select regions of the hardmask layer are removed to expose select regions of the metal lines of the lower metallization layer. Metal vias are formed on the select regions of the metal lines of the lower metallization layer.
摘要翻译：描述了用于后端线路（BEOL）互连的网格自对准金属通孔处理方案。在一个示例中，一种制造用于半导体管芯的互连结构的方法包括：在衬底上方形成包括交替的金属线和电介质线的下金属化层，所述电介质线位于金属线上方。硬掩模层形成在下金属化层的金属线上，在下金属化层的电介质线之间并与其共面。光栅结构形成在下部金属化层的交替金属线和电介质线的上方并与其正交。在光栅结构上方形成掩模。选择硬掩模层的选择区域以暴露下金属化层的金属线的选定区域。金属通孔形成在下金属化层的金属线的选定区域上。

6. 发明申请

WO2019066768A1 DIRECTIONAL SPACER REMOVAL FOR INTEGRATED CIRCUIT STRUCTURES 审中-公开
公开(公告)号：WO2019066768A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053358
申请日：2017-09-26
申请人： INTEL CORPORATION
发明人： GULER, Leonard P. , TAN, Elliot
IPC分类号： H01L27/12 , H01L27/088 , H01L21/8234 , H01L21/84
摘要： Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.

7. 发明申请

WO2017111819A1 GATE ISOLATION IN NON-PLANAR TRANSISTORS 审中-公开
标题翻译：非平面晶体管中的隔离栅
公开(公告)号：WO2017111819A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000377
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： GULER, Leonard P. , BHIMARASETTI, Gopinath , SHARMA, Vyom , HAFEZ, Walid M. , AUTH, Christopher P.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，该装置包括：相互平行的第一和第二半导体鳍片; 第一栅极，在所述第一鳍片上，包括在所述第一鳍片和所述第二鳍片之间的第一栅极部分; 在所述第二翅片上的第二闸门，所述第二闸门包括在所述第一翅片和所述第二翅片之间的第二闸门部分; 沿着所述第一栅极部分的第一面延伸的第一氧化物层，沿着所述第二栅极部分的第二面延伸的第二氧化物层以及将所述第一氧化物层和第二氧化物层彼此连接的第三氧化物层; 以及第一和第二门部分之间的绝缘材料; 其中所述第一，第二和第三氧化物层各自包括氧化物材料并且所述绝缘材料不包括所述氧化物材料。这里描述了其他实施例。

8. 发明申请

WO2019035837A1 INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE 审中-公开
公开(公告)号：WO2019035837A1
公开(公告)日：2019-02-21
申请号：PCT/US2017/047409
申请日：2017-08-17
申请人： INTEL CORPORATION
发明人： GULER, Leonard P. , GUHA, Biswajeet , ARMSTRONG, Mark , GHANI, Tahir , HSU, William
IPC分类号： H01L27/088 , H01L27/02 , H01L29/06
摘要： Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

9. 发明申请

WO2018004680A1 SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES 审中-公开
标题翻译：自对准栅极触发器和FINFET器件
公开(公告)号：WO2018004680A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040804
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LIAO, Szuya S. , GUHA, Biswajeet , GHANI, Tahir , KENYON, Christopher N. , GULER, Leonard P.
IPC分类号： H01L29/78
CPC分类号： H01L27/0924 , H01L21/76895 , H01L21/823821 , H01L21/823878 , H01L23/535 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.
摘要翻译：描述了自对准的栅极边缘触发和finFET器件以及制造自对准的栅极边缘触发器和finFET器件的方法。在示例中，半导体结构包括设置在衬底上方并且穿过沟槽隔离区域的最上表面突出的多个半导体鳍。栅极结构设置在多个半导体鳍上。栅极结构限定多个半导体鳍片中的每一个中的沟道区域。源极和漏极区位于栅极结构的相对侧的多个半导体鳍中的每一个的沟道区的相对端上。该半导体结构还包括多个栅极边缘隔离结构。多个栅极边缘隔离结构中的各个栅极边缘隔离结构与多个半导体鳍片中的各个半导体鳍片交替。

10. 发明申请

WO2017052576A1 SEMICONDUCTOR DEVICES INCLUDING A RECESSED ISOLATION FILL, AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：包含分离隔离膜的半导体器件及其制造方法
公开(公告)号：WO2017052576A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052162
申请日：2015-09-25
申请人： INTEL CORPORATION , LINDERT, Nick , STEIGERWALD, Joseph M. , GULER, Leonard P.
发明人： LINDERT, Nick , STEIGERWALD, Joseph M. , GULER, Leonard P.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： Technologies for manufacturing semiconductor devices including isolation structures having a recessed isolation fill are disclosed. In some embodiments the technologies include methods for forming a recessed isolation fill within an isolation trench that electrically isolate at least two active transistor gates from one another. In further embodiments, methods for forming local interconnects in the isolation trench are also disclosed. Semiconductor devices including active transistors isolated by a recessed isolation fill and systems including such devices are also described.
摘要翻译：公开了包括具有凹陷隔离填充物的隔离结构的半导体器件的制造技术。在一些实施例中，这些技术包括在隔离沟槽内形成凹陷的隔离填充物的方法，该隔离沟槽将至少两个有源晶体管栅极彼此电隔离。在另外的实施例中，还公开了用于在隔离沟槽中形成局部互连的方法。还描述了包括通过凹陷隔离填充物隔离的有源晶体管和包括这种器件的系统的半导体器件。

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