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1. 发明申请

WO2012134532A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开
标题翻译：向导友好指示格式及其执行
公开(公告)号：WO2012134532A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/054303
申请日：2011-09-30
申请人： INTEL CORPORATION , VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
发明人： VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译：一种向量友好的指令格式及其执行。根据本发明的一个实施例，处理器被配置为执行指令集。指令集包括向量友好指令格式。向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作，基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段，在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

2. 发明申请

WO2022212213A1 APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR DOWNCONVERTING A TILE ROW AND INTERLEAVING WITH A REGISTER 审中-公开
公开(公告)号：WO2022212213A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/022040
申请日：2022-03-25
申请人： INTEL CORPORATION
发明人： ADELMAN, Menachem , VALENTINE, Robert , GRADSTEIN, Amit , TOWNER, Daniel , CHARNEY, Mark
IPC分类号： G06F9/30 , G06F17/16 , G06N3/063 , G06F9/30025 , G06F9/30098 , G06F9/3016
摘要： Systems, methods, and apparatuses relating to interleaving data values. An embodiment includes decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and execution circuitry to execute the decoded instruction according to the opcode.

3. 发明申请

WO2022203785A1 INSTRUCTION AND LOGIC FOR SUM OF ABSOLUTE DIFFERENCES 审中-公开
公开(公告)号：WO2022203785A1
公开(公告)日：2022-09-29
申请号：PCT/US2022/016888
申请日：2022-02-18
申请人： INTEL CORPORATION
发明人： AGGARWAL, Deepti , ESPIG, Michael , VALENTINE, Robert , CHARNEY, Mark
IPC分类号： G06F9/38 , G06F9/30
摘要： In an embodiment, a processor includes: a fetch circuit to fetch instructions, the instructions including a sum of absolute differences (SAD) instruction; a decode circuit to decode the SAD instruction; and an execution circuit to, during an execution of the decoded SAD instruction, generate an SAD output vector based on a plurality of input vectors, the SAD output vector including a plurality of absolute differences values. Other embodiments are described and claimed.

4. 发明申请

WO2022066358A1 APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR LOADING DATA AND PADDING INTO A TILE OF A MATRIX OPERATIONS ACCELERATOR 审中-公开
公开(公告)号：WO2022066358A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/047825
申请日：2021-08-26
申请人： INTEL CORPORATION
发明人： HUGHES, Christoper J. , HEINECKE, Alexander , VALENTINE, Robert , ADELMAN, Menachem , GEORGANAS, Evangelos , CHARNEY, Mark
IPC分类号： G06F9/30
摘要： Systems, methods, and apparatuses relating to one or more instructions that load data into a tile register and pad a row (or column) with a pad value from a padding circuit are described. In one embodiment, a system includes a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a tile register that represents a two-dimensional matrix coupled to the matrix operations accelerator circuit, and a coupling to a memory, a padding circuit coupled to the tile register, and a hardware processor core including a decoder, of the hardware processor core coupled to the matrix operations accelerator circuit, to decode a single instruction into a decoded single instruction, the single instruction comprising a first field that identifies the tile register, a second field that identifies data elements in the memory, and an opcode, the opcode to indicate an execution circuit of the hardware processor core is to cause a load of the data elements from the memory into the tile register and the padding circuit to pad a proper subset of elements of the tile register with a same value, and the execution circuit of the hardware processor core to execute the decoded single instruction according to the opcode.

5. 发明申请

WO2005041047A2 METHOD AND APPARATUS FOR EFFICIENT ORDERED STORES OVER AN INTERCONNECTION NETWORK 审中-公开
标题翻译：通过互连网络实现有效订购存储的方法和装置
公开(公告)号：WO2005041047A2
公开(公告)日：2005-05-06
申请号：PCT/US2004/034147
申请日：2004-10-15
申请人： INTEL CORPORATION (a Delaware Corporation) , CHARNEY, Mark , RAJWAR, Ravi , AHUJA, Pritpal , MATTINA, Matt
发明人： CHARNEY, Mark , RAJWAR, Ravi , AHUJA, Pritpal , MATTINA, Matt
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0837 , G06F12/084
摘要： A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requestor identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.
摘要翻译：物理分布式高速缓冲存储器系统包括互连网络，第一级高速缓存存储器片和第二级高速缓存存储器片。第一级缓存存储器片耦合到互连网络以生成标记的有序存储请求。每个标记的有序存储请求都具有包括请求者标识和存储序列令牌的标签。第二级高速缓存存储器片耦合到互连网络，以响应于标记的有序存储请求的每个标签，跨物理分布的高速缓冲存储器系统按顺序执行有序存储请求。

6. 发明公开

EP4141659A1 BFLOAT16 ARITHMETIC INSTRUCTIONS 审中-实审
公开(公告)号：EP4141659A1
公开(公告)日：2023-03-01
申请号：EP22188069.3
申请日：2022-08-01
申请人： INTEL Corporation
发明人： ADELMANN, Menachem , HEINECKE, Alexander , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit , CHARNEY, Mark , GEORGANAS, Evangelos , KALAMKAR, Dhiraj , HUGHES, Christopher , ANDERSON, Cristina
IPC分类号： G06F9/30
摘要： Techniques for performing arithmetic operations on BF16 values are described. An exemplary instruction includes fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on BF16 data elements in that data element position in BF16 format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand.

7. 发明公开

EP4020179A1 APPARATUS AND METHOD FOR COMPLEX MATRIX TRANSPOSE AND MULTIPLY 审中-公开
公开(公告)号：EP4020179A1
公开(公告)日：2022-06-29
申请号：EP21198492.7
申请日：2021-09-23
申请人： INTEL Corporation
发明人： ADELMAN, Menachem , VALENTINE, Robert , TOWNER, Daniel , GRADSTEIN, Amit , CHARNEY, Mark
IPC分类号： G06F9/30
摘要： An apparatus and method for complex matrix transpose and multiply. For example, one embodiment of a processor comprises: a decoder to decode a first complex matrix multiplication and transpose instruction including a first source operand to identify a first plurality of real and imaginary values in a first complex source matrix, a second source operand to identify a second plurality of real and imaginary values in a second complex source matrix, and a first destination operand to identify a result matrix with real and imaginary values; execution circuitry to execute the first complex matrix transpose and multiplication instruction, the execution circuitry comprising transpose hardware logic to transpose at least one of the source matrices, parallel multiplication circuitry to multiply real values from the first plurality of real and imaginary values with corresponding real values from the second plurality of real and imaginary values to generate a first plurality of real products, to multiply imaginary values from the first plurality of real and imaginary values with corresponding imaginary values from the second plurality of real and imaginary values to generate a second plurality of real products; and addition/subtraction circuitry to subtract each real product in the second plurality of real products from a corresponding real product in the first plurality of real products to produce a corresponding real value in the result matrix.

8. 发明公开

EP3805921A2 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 有权
公开(公告)号：EP3805921A2
公开(公告)日：2021-04-14
申请号：EP20199439.9
申请日：2011-09-30
申请人： INTEL Corporation
发明人： VALENTINE, Robert C. , SAN ADRIAN, Jesus Corbal , SANS, Roger Espasa , CAVIN, Robert D. , TOLL, Bret L. , DURAN, Santiago Galan , WIEDEMEIER, Jeffrey G. , SAMUDRALA, Sridhar , GIRKAR, Milind Baburao , GROCHOWSKI, Edward Thomas , HALL, Jonathan Cannon , BRADFORD, Dennis R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

9. 发明公开

EP4315043A1 INSTRUCTION AND LOGIC FOR SUM OF ABSOLUTE DIFFERENCES 审中-实审
公开(公告)号：EP4315043A1
公开(公告)日：2024-02-07
申请号：EP22776285.3
申请日：2022-02-18
申请人： INTEL Corporation
发明人： AGGARWAL, Deepti , ESPIG, Michael , VALENTINE, Robert , CHARNEY, Mark
IPC分类号： G06F9/38 , G06F9/30

10. 发明公开

EP4273694A3 INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 审中-实审
公开(公告)号：EP4273694A3
公开(公告)日：2024-01-24
申请号：EP23199193.6
申请日：2021-09-24
申请人： Intel Corporation
发明人： HEINECKE, Alexander , MELLEMPUDI, Naveen , VALENTINE, Robert , CHARNEY, Mark , HUGHES, Christopher , GEORGANAS, Evangelos , SPERBER, Zeev , GRADSTEIN, Amit , RUBANOVICH, Simon
IPC分类号： G06F9/30
摘要： The present disclosure provides an apparatus, wherein the apparatus comprises a plurality of memory controllers; a level-two (L2) cache memory coupled to the plurality of memory controllers; a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores and a plurality of levels of cache memory, the cores including circuitry to perform operations corresponding to an instruction, the instruction to identify a source register; that is to include a plurality of half-precision floating-point data elements and to identify a destination register, wherein the half-precision floating-point data elements are 16-bit data elements, the operations including to: convert the plurality of half-precision floating-point data elements to a plurality of corresponding 8-bit floating-point data elements, wherein, when one or more of the half-precision floating-point data elements are normal numbers, conversion of the one or more normal numbers to one or more corresponding 8-bit floating-point data elements is to be performed according to a round to nearest even rounding mode, and the one or more corresponding 8-bit floating-point data element are each to include one sign bit, five exponent bits, and two mantissa bits; and store the plurality of 8-bit floating-point data elements in the destination register.

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