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1. 发明申请

WO2001016715A1 BRANCH INSTRUCTIONS IN A MULTITHREADED PARALLEL PROCESSING SYSTEM 审中-公开
标题翻译：分支指令在多个并行的并行处理系统中
公开(公告)号：WO2001016715A1
公开(公告)日：2001-03-08
申请号：PCT/US2000/023983
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/32
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor can execute a computer instruction that is a branch instruction that causes an execution stream to branch to an instruction at an address specified in the instruction if a state of a specified state name of the processor is a specified value.
摘要翻译：描述诸如并行硬件的多线程处理器（12）之类的处理器。如果处理器的指定状态名称的状态是指定值，则处理器可以执行作为分支指令的计算机指令，该分支指令使执行流分支到指令中指定的地址处的指令。

2. 发明申请

WO2013048532A1 USING A GRAPHICS ENGINE TO PROCESS PRINT REQUESTS 审中-公开
标题翻译：使用图形引擎来处理打印请求
公开(公告)号：WO2013048532A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054489
申请日：2011-10-01
申请人： INTEL CORPORATION , FALLON, Michael, F. , WILDE, Myles , ADILETTA, Matthew, J. , TAYLOR, Stewart
发明人： FALLON, Michael, F. , WILDE, Myles , ADILETTA, Matthew, J. , TAYLOR, Stewart
IPC分类号： G06F3/12 , G06F9/06 , G06F9/30 , G06F13/38
CPC分类号： G06F3/1205 , G03G15/50 , G03G15/5083 , G06F3/122 , G06F3/1247 , G06F3/126 , G06F3/1279 , G06F3/1284 , G06F13/38 , G06K15/1856
摘要： Systems and methods of operating a computing system may involve utilizing an graphics engine to complete a print request. Upon receiving a request to print a scheduling management application may direct an application programming interface call to the graphics engine, and the graphics engine may process a print imaging instruction.
摘要翻译：操作计算系统的系统和方法可以涉及利用图形引擎来完成打印请求。在接收到打印调度管理应用程序的请求时，可以将应用编程接口调用指向图形引擎，并且图形引擎可以处理打印成像指令。

3. 发明申请

WO2013048509A1 SECURE PRINTING BETWEEN PRINTER AND PRINT CLIENT DEVICE 审中-公开
标题翻译：打印机和打印客户端设备之间的安全打印
公开(公告)号：WO2013048509A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054453
申请日：2011-09-30
申请人： INTEL CORPORATION , FALLON, Michael, F. , WILDE, Myles , ADILETTA, Matthew, J.
发明人： FALLON, Michael, F. , WILDE, Myles , ADILETTA, Matthew, J.
IPC分类号： G06F3/12 , G06F21/24 , G06F21/20
CPC分类号： G06F21/608 , G06F3/1222 , G06F3/1238 , G06F21/57 , G06K15/4095
摘要： Systems and methods of operating a computing system may involve securely printing a print document sent from a client device to a target printer. In one example, the method may include verifying an operating environment of the target printer and generating a plurality of security keys to implement asymmetric encryption of the print document.
摘要翻译：操作计算系统的系统和方法可以包括将从客户端设备发送的打印文档安全地打印到目标打印机。在一个示例中，该方法可以包括验证目标打印机的操作环境并生成多个安全密钥以实现打印文档的非对称加密。

4. 发明申请

WO2018017258A1 TECHNOLOGIES FOR SWITCHING NETWORK TRAFFIC IN A DATA CENTER 审中-公开
标题翻译：在数据中心交换网络业务的技术
公开(公告)号：WO2018017258A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/038552
申请日：2017-06-21
申请人： INTEL CORPORATION
发明人： ADILETTA, Matthew, J. , GORIUS, Aaron , WILDE, Myles , CROCKER, Michael, T.
IPC分类号： H04L12/861 , H04L12/879 , H04Q11/00
摘要： Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.
摘要翻译：交换网络流量的技术包括网络交换机。网络交换机包括耦合到一个或多个处理器的一个或多个处理器和通信电路。通信电路能够切换多个链路层协议的网络流量。另外，网络交换机包括存储指令的一个或多个存储器设备，所述指令在被执行时使得网络交换机利用通信电路通过光学连接来接收要被转发的网络流量，并且确定所接收的网络的链路层协议交通。这些指令还使网络交换机根据所确定的链路层协议转发网络业务。其他实施例也被描述和要求保护。

5. 发明申请

WO2001018646A1 BRANCH INSTRUCTION FOR MULTITHREADED PROCESSOR 审中-公开
标题翻译：多用途加工商分支指导
公开(公告)号：WO2001018646A1
公开(公告)日：2001-03-15
申请号：PCT/US2000/023992
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/38
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor (12) is described. The processor (12) includes a general purpose processor that coordinates system functions and a plurality of microengines (22a-22f) that support multiple hardware threads or contexts. The processor (12) also includes a memory control system (16) that has a first memory controller (26a) that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller (26b) that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译：描述了一种基于并行硬件的多线程处理器（12）。处理器（12）包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微引擎（22a-22f）。处理器（12）还包括存储器控制系统（16），该存储器控制系统（16）具有第一存储器控制器（26a），该第一存储器控制器基于存储器参考是指向偶数存储器还是存储器的奇数存储器，并且第二存储器控制器（26b），其基于存储器引用是读取引用还是写入引用来优化存储器引用。还公开了基于执行上下文的切换和分支的指令。

6. 发明申请

WO2001016714A1 FAST WRITE INSTRUCTION FOR MICRO ENGINE USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 审中-公开
标题翻译：用于多路并行处理器架构的微型发动机的快速写入指令
公开(公告)号：WO2001016714A1
公开(公告)日：2001-03-08
申请号：PCT/US2000/024000
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/312
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A method of operating a processor (12) including receiving data in a processing thread having a processing thread number and shifting the data into a register corresponding to the processing thread number.
摘要翻译：一种操作处理器（12）的方法，包括在具有处理线程号的处理线程中接收数据，并将数据移位到与处理线程号相对应的寄存器中。

7. 发明申请

WO2018017261A1 TECHNIQUES TO PROCESS PACKETS IN A DUAL-MODE SWITCHING ENVIRONMENT 审中-公开
标题翻译：在双模式切换环境中处理分组的技术
公开(公告)号：WO2018017261A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/038652
申请日：2017-06-22
申请人： INTEL CORPORATION
发明人： GORIUS, Aaron , WILDE, Myles , ADILETTA, Matthew, J.
IPC分类号： H04L12/931 , H04L12/933 , H04L12/861 , H04Q11/00
摘要： Various embodiments are generally directed to an apparatus, method and other techniques to receive a packet via an optical fabric, the packet comprising a switch mode indicator, determine a switch mode for the packet based on the switch mode indicator, and process the packet in accordance with a first protocol or a second protocol based on the switch mode.
摘要翻译：各种实施例通常涉及经由光学结构接收分组的装置，方法和其他技术，所述分组包括开关模式指示符，基于开关模式来确定分组的开关模式指示符，并且根据基于切换模式的第一协议或第二协议处理分组。

8. 发明申请

WO2001016769A1 SRAM CONTROLLER FOR PARALLEL PROCESSOR ARCHITECTURE 审中-公开
标题翻译：用于并行处理器架构的SRAM控制器
公开(公告)号：WO2001016769A1
公开(公告)日：2001-03-08
申请号：PCT/US2000/022653
申请日：2000-08-17
申请人： INTEL CORPORATION , ADILETTA, Matthew, J. , WHEELER, William , REDFIELD, James , CUTTER, Daniel , WOLRICH, Gilbert
发明人： ADILETTA, Matthew, J. , WHEELER, William , REDFIELD, James , CUTTER, Daniel , WOLRICH, Gilbert
IPC分类号： G06F13/16
CPC分类号： G06F13/1642
摘要： A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
摘要翻译：用于随机存取存储器的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。地址和命令队列包括存储读取存储器引用的读取队列。控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用排队。

9. 发明申请

WO2001016758A3 DOUBLE SHIFT INSTRUCTION FOR MICRO ENGINE USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2001016758A3
公开(公告)日：2001-03-08
申请号：PCT/US2000/023982
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/315
摘要： A method of operating a processor comprises concatenating a first word and a second word to produce an intermediate result. An ALU (76a) shifts the intermediate result by a specified shift amount and stores, in a register (76b), the shifted intermediate result in a third word.

10. 发明授权

EP1236088B9 REGISTER SET USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 有权
标题翻译：用于多线程并行处理器架构的寄存器组
公开(公告)号：EP1236088B9
公开(公告)日：2008-10-08
申请号：EP00959711.3
申请日：2000-08-31
申请人： Intel Corporation
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文（THREAD_3 ... THREAD_0）的多个微引擎。处理器维护执行线程（THREAD_3 ... THREAD_0）。执行线程（THREAD_3 ... THREAD_0）访问组织成多个相对可寻址的，每个线程相对可寻址的寄存器窗口（THREAD_3 ... THREAD_0）的寄存器组。

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