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1. 发明申请

WO0233706A3 NOISE SUPPRESSION FOR OPEN BIT LINE DRAM ARCHITECTURES 审中-公开
标题翻译：用于打开位线DRAM架构的噪声抑制
公开(公告)号：WO0233706A3
公开(公告)日：2003-04-17
申请号：PCT/US0131159
申请日：2001-10-03
申请人： INTEL CORP , LU SHIH-LIEN , SOMASEKHAR DINESH , DE VIVEK
发明人： LU SHIH-LIEN , SOMASEKHAR DINESH , DE VIVEK
IPC分类号： G11C20060101 , G11C7/02 , G11C11/4094 , G11C11/4097 , H01L20060101 , G11C7/12 , G11C7/14 , G11C7/18 , G11C11/4099 , H01L27/108
CPC分类号： G11C11/4097 , G11C7/02 , G11C11/4094
摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
摘要翻译：开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。在一种方法中，提供虚拟单元和参考单元用于执行信号注入。本发明的原理特别适合于在嵌入式DRAM结构中使用，其中各个单元内的低电荷存储容量降低可实现的信号电压电平。

2. 发明申请

WO2011146823A3 METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE 审中-公开
标题翻译：在支持低功耗状态的系统中使用高速缓存存储器的方法和装置
公开(公告)号：WO2011146823A3
公开(公告)日：2012-04-05
申请号：PCT/US2011037319
申请日：2011-05-20
申请人： INTEL CORP , WILKERSON CHRISTOPHER B , WU WEI , ALAMELDEEN ALAA R , LU SHIH-LIEN , CHISHTI ZESHAN A , SOMASEKHAR DINESH
发明人： WILKERSON CHRISTOPHER B , WU WEI , ALAMELDEEN ALAA R , LU SHIH-LIEN , CHISHTI ZESHAN A , SOMASEKHAR DINESH
IPC分类号： G06F12/08 , G06F1/32 , G06F11/10
CPC分类号： G06F11/1064
摘要： A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.
摘要翻译：提供了一种使用具有低存储和复杂度开销的多位错误校正码（ECC）的高速缓冲存储器系统。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。

3. 发明申请

WO2007038033A3 METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION 审中-公开
标题翻译：用于晚时间转换检测的方法和设备
公开(公告)号：WO2007038033A3
公开(公告)日：2007-06-21
申请号：PCT/US2006036153
申请日：2006-09-14
申请人： INTEL CORP , GROCHOWSKI EDWARD , WILKERSON CHRIS , LU SHIH-LIEN , ANNAVARAM MURALI
发明人： GROCHOWSKI EDWARD , WILKERSON CHRIS , LU SHIH-LIEN , ANNAVARAM MURALI
IPC分类号： H03K5/13 , G01R31/317
CPC分类号： G01R31/31922 , G01R31/31726 , H03K5/1534 , H04L7/0083 , H04L7/033
摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
摘要翻译：两个锁存器在时钟信号的转换处存储数据信号的状态。比较逻辑比较两个锁存器的输出并产生一个信号来指示输出是相等还是不相等。描述并要求保护使用锁存器和比较逻辑的系统。

4. 发明专利

DE69918718T2 未知
公开(公告)号：DE69918718T2
公开(公告)日：2005-08-04
申请号：DE69918718
申请日：1999-09-15
申请人： INTEL CORP
发明人： YE YIBIN , LU SHIH-LIEN , DE K , NARENDRA SIVA
IPC分类号： H03K5/04 , H03K5/13 , H03K19/017 , H03K3/00 , H03K3/037 , H03K17/687 , H03K19/00 , H03K19/01 , H03K19/0175

5. 发明申请

WO03027857A2 HIDING REFRESH OF MEMORY AND REFRESH-HIDDEN MEMORY 审中-公开
标题翻译：隐藏更新记忆和更新隐藏的记忆
公开(公告)号：WO03027857A2
公开(公告)日：2003-04-03
申请号：PCT/US0231158
申请日：2002-09-27
申请人： INTEL CORP
发明人： LAI KONRAD , LU SHIH-LIEN , SOMASEKHAR DINESH
IPC分类号： G06F12/08
CPC分类号： G06F12/0893
摘要： The present invention is in the field of memory architecture and management. More particularly, the present invention provides a method, apparatus, system, and machine-readable medium to hide refresh cycles of a memory array such as dynamic random access memory.
摘要翻译：本发明属于存储器体系结构和管理领域。更具体地说，本发明提供了一种隐藏诸如动态随机存取存储器之类的存储器阵列的刷新周期的方法，装置，系统和机器可读介质。

6. 发明公开

EP1142115A4 A METHOD AND APPARATUS FOR REDUCING SIGNAL TRANSMISSION DELAY USING SKEWED GATES 有权
标题翻译：方法和装置以降低信号传输延迟使用VONVERSCHIEBEGATTERN
公开(公告)号：EP1142115A4
公开(公告)日：2002-06-05
申请号：EP99946988
申请日：1999-09-15
申请人： INTEL CORP
发明人： YE YIBIN , LU SHIH-LIEN , DE VIVEK K , NARENDRA SIVA
IPC分类号： H03K5/04 , H03K5/13 , H03K19/017 , H03K3/00 , H03K3/037 , H03K17/687 , H03K19/00 , H03K19/01 , H03K19/0175
CPC分类号： H03K5/04 , H03K5/133 , H03K19/01707
摘要： Alternately skewed gates (1509) to reduce signal transmission delay. For one embodiment, an integrated circuit includes a chain of gates (1505, 1506, 1507, 1508) alternately skewed for fast rise and fast fall. Pulse encoding logic (1510) coupled to the chain of gates pulse encodes a signal to be provided to and transmitted by the chain of alternately skewed gates.

7. 发明公开

EP3111449A4 WRITE OPERATIONS IN SPIN TRANSFER TORQUE MEMORY 有权转让
公开(公告)号：EP3111449A4
公开(公告)日：2017-10-25
申请号：EP15755970
申请日：2015-02-02
申请人： INTEL CORP
发明人： NAEIMI HELIA , LU SHIH-LIEN , AUGUSTINE CHARLES
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C7/1009 , G11C11/1657

8. 发明专利

AT426899T 未知
公开(公告)号：AT426899T
公开(公告)日：2009-04-15
申请号：AT02797727
申请日：2002-08-01
申请人： INTEL CORP
发明人： LU SHIH-LIEN , SOMASEKHAR DINESH , DE VIVEK
IPC分类号： G11C11/408 , G11C11/4097
摘要： The word-lines and/or bit-lines in a memory are physically arranged to reduce capacitive coupling between signal lines and reference lines. In one embodiment the two bit lines connected to a single sense amplifier are physically separated from each other by bit lines connected to other sense amplifiers. In another embodiment the word-lines are separated from each other by placing them in different metallization layers. In a particular embodiment a single word-line has different portions disposed in different metallization layers.

9. 发明专利

DE112006002337T5 未知
公开(公告)号：DE112006002337T5
公开(公告)日：2008-06-19
申请号：DE112006002337
申请日：2006-09-14
申请人： INTEL CORP
发明人： GROCHOWSKI EDWARD , WILKERSON CHRIS , LU SHIH-LIEN , ANNAVARAM MURALI
IPC分类号： H03K5/13 , G01R31/317
摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

10. 发明专利

GB2406199A Reducing noise during a read operation in a dynamic random access memory device 未知
公开(公告)号：GB2406199A
公开(公告)日：2005-03-23
申请号：GB0425950
申请日：2001-10-03
申请人： INTEL CORP
发明人： LU SHIH-LIEN , SOMASEKHAR DINESH , DE VIVEK
IPC分类号： G11C20060101 , G11C7/02 , G11C11/4094 , G11C11/4097 , H01L20060101
摘要： A method for reducing noise during a read operation in a DRAM device in which the DRAM device comprises a common differential sense amplifier 64 coupled to first and second bit lines 66, 68, a memory cell 70 coupled to the first bit line 66 and a first word line 72, a reference cell 76 coupled to the second bit line 68 and a second word line 80, a first dummy cell 82 coupled to the first bit line and a third word line 86, and a second dummy cell 84 coupled to the second bit line 68 and the third word line 86. The method comprises activating and then subsequently deactivating the first and second dummy cells 82, 84 using the third word line, and then simultaneously activating the memory and reference cells 70, 76 using the first and second word lines 72, 80. The activation and deactivation steps could include changing a signal on the word lines 72, 80. Deactivating the first and second dummy cells could inject first signals of a first polarity into the bit lines and activating the memory and reference cells 70, 76 could inject second signals of different polarity, but equal in magnitude to the first signals, into the bit lines 66, 68.

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