专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012061091A3 ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE 审中-公开
标题翻译：封装裸片，含有该封装的微电子封装以及制造所述微电子封装的方法
公开(公告)号：WO2012061091A3
公开(公告)日：2012-08-23
申请号：PCT/US2011057594
申请日：2011-10-25
申请人： INTEL CORP , GUZEK JOHN S , SANKMAN ROBERT L , ICHIKAWA KINYA , TOMITA YOSHIHIRO , KUBOTA JIRO
发明人： GUZEK JOHN S , SANKMAN ROBERT L , ICHIKAWA KINYA , TOMITA YOSHIHIRO , KUBOTA JIRO
IPC分类号： H01L23/28 , H01L21/56 , H01L23/48
CPC分类号： H01L23/3114 , H01L23/3128 , H01L23/3185 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/12105 , H01L2225/1035 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.
摘要翻译：封装管芯（100,401）包括具有第一表面（111），相对的第二表面（112）和居间侧表面（113）的衬底（110,510），其中有源器件位于第一表面基质。有源器件通过由多个电绝缘层（125,525）彼此分开的多个导电层（120,520）连接。保护帽（130,530）位于衬底的第一表面上，包含暴露在其表面（131）处的互连结构（140）。在另一个实施例中，微电子封装（200）包括封装衬底（250），封装衬底（250）具有嵌入其中的如上所述的封装管芯（100）。

2. 发明专利

DE60219779D1 未知
公开(公告)号：DE60219779D1
公开(公告)日：2007-06-06
申请号：DE60219779
申请日：2002-02-21
申请人： INTEL CORP
发明人： KUBOTA JIRO , TAKAHASHI KENJI
IPC分类号： H01L23/485 , H01L21/60 , H01L21/603 , H05K3/24 , H05K3/34
摘要： A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

3. 发明专利

AT360888T 未知
公开(公告)号：AT360888T
公开(公告)日：2007-05-15
申请号：AT02713638
申请日：2002-02-21
申请人： INTEL CORP
发明人： KUBOTA JIRO , TAKAHASHI KENJI
IPC分类号： H01L21/60 , H01L23/485 , H05K3/24 , H05K3/34 , H01L21/603
摘要： A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

4. 发明专利

AU2002245476A1 Fluxless flip chip interconnection 未知
公开(公告)号：AU2002245476A1
公开(公告)日：2002-10-15
申请号：AU2002245476
申请日：2002-02-21
申请人： INTEL CORP
发明人： TAKAHASHI KENJI , KUBOTA JIRO
IPC分类号： H01L21/60 , H01L23/485 , H05K3/24 , H05K3/34 , H01L21/603 , B23K20/02 , H01L21/56 , H01L21/00
摘要： A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

5. 发明专利

MY122941A FLUXLESS FLIP CHIP INTERCONNECTION. 未知
公开(公告)号：MY122941A
公开(公告)日：2006-05-31
申请号：MYPI20020774
申请日：2002-03-05
申请人： INTEL CORP
发明人： TAKAHASHI KENJI , KUBOTA JIRO
IPC分类号： H01L21/60 , H01L23/485 , H05K3/24 , H05K3/34
摘要： A FLIP CHIP METHOD OF JOINING A CHIP AND A SUBSTRATE IS DESCRIBED. A THERMO-COMPRESSION BONDER IS UTILIZED TO ALIGN THE CHIP (325) AND SUBSTRATE (315) AND APPLY A CONTACT FORCE TO HOLD SOLDER BUMPS (305) ON THE SUBSTRATE (315) AGAINST METAL BUMPS (320) ON THE CHIP (325). THE CHIP (325) IS RAPIDLY HEATED FROM ITS NON-NATIVE SIDE BY A PULSE HEATER IN THE HEAD OF THE BONDER UNTIL THE RE-FLOW FLOW TEMPERATURE OF THE SOLDER BUMPS (305) IS REACHED. PROXIMATE WITH REACHING THE RE-FLOW TEMPERATURE AT THE SOLDER BUMPS (305), THE CONTACT FORCE IS RELEASED. THE SOLDER IS HELD ABOVE ITS REFLOW TEMPERATURE FOR SEVERAL SECONDS TO FACILITATE WETTING OF THE SUBSTRATE'S METAL PROTRUSIONS AND JOINING. METAL CAPS COMPRISED OF A NOBLE METAL SUCH AS PALLADIUM IS APPLIED TO THE SURFACE OF THE METAL BUMPS (320) TO PREVENT THE METAL BUMPS (WHICH GENERALLY COMPRISE A HIGHLY-CONDUCTIVE AND HIGHLY-REACTIVE METAL SUCH AS COPPER) FROM OXIDIZING IN THE ELEVATED TEMPERATURES JUST PRIOR TO AND DURING THE RE-FLOW OPERATION. FIGURE 3

6. 发明专利

HK1061741A1 Fluxless flip chip interconnection 未知
公开(公告)号：HK1061741A1
公开(公告)日：2004-09-30
申请号：HK04104564
申请日：2004-06-25
申请人： INTEL CORP
发明人： KUBOTA JIRO , TAKAHASHI KENJI
IPC分类号： H01L20060101 , H01L21/60 , H01L23/485 , H05K3/24 , H05K3/34
摘要： A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

7. 发明公开

EP2636063A4 ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE 审中-公开
标题翻译：封装芯片，微电子包才能和方法用于制造这种微电子封装
公开(公告)号：EP2636063A4
公开(公告)日：2015-11-11
申请号：EP11838496
申请日：2011-10-25
申请人： INTEL CORP
发明人： GUZEK JOHN S , SANKMAN ROBERT L , ICHIKAWA KINYA , TOMITA YOSHIHIRO , KUBOTA JIRO
IPC分类号： H01L23/28 , H01L21/56 , H01L21/60 , H01L23/31 , H01L23/48 , H01L23/485 , H01L25/10
CPC分类号： H01L23/3114 , H01L23/3128 , H01L23/3185 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/12105 , H01L2225/1035 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/3511 , H01L2924/00

8. 发明专利

DE60219779T2 未知
公开(公告)号：DE60219779T2
公开(公告)日：2007-12-27
申请号：DE60219779
申请日：2002-02-21
申请人： INTEL CORP
发明人： KUBOTA JIRO , TAKAHASHI KENJI
IPC分类号： H01L23/485 , H01L21/60 , H01L21/603 , H05K3/24 , H05K3/34
摘要： A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

9. 发明专利

AU7987400A Advanced flip-chip join package 未知
公开(公告)号：AU7987400A
公开(公告)日：2001-05-08
申请号：AU7987400
申请日：2000-09-27
申请人： INTEL CORP
发明人： ISHIDA KENZO , TAKAHASHI KENJI , KUBOTA JIRO
IPC分类号： H01L23/29 , H01L21/56 , H01L21/60 , H01L23/31
摘要： The present invention provides a method of attaching an integrated circuit die to a substrate. The method includes applying solder bumps to contact areas, and placing the inverted integrated circuit die in a desired location such that the solder bumps are in contact with contact areas of the integrated circuit die and the substrate. The solder bumps are heated to mount the die, such that the bumps form a connection between the substrate and the integrated circuit. The gap between the die and the substrate is underfilled by injecting a molding compound into a molding die positioned over the mounted integrated circuit die.

10. 发明专利

AU2343797A Multilayer solder interconnection structure 未知
公开(公告)号：AU2343797A
公开(公告)日：1997-10-22
申请号：AU2343797
申请日：1997-03-10
申请人： INTEL CORP
发明人： MASHIMOTO YOHKO , INOUE SHUJI , KUBOTA JIRO , KURODA MASHAHIRO
IPC分类号： H01L21/56 , H01L21/60 , H01L23/48 , H01L23/52 , H01L29/40
摘要： An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式