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1. 发明申请

WO2013101078A8 SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA 审中-公开
标题翻译：支持无数据的统计所有权
公开(公告)号：WO2013101078A8
公开(公告)日：2013-09-06
申请号：PCT/US2011067865
申请日：2011-12-29
申请人： INTEL CORP , GIBERT CODINA ENRIC , LATORRE FERNANDO , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MEYREM , KOTSELIDIS CHRISTOS E , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
发明人： GIBERT CODINA ENRIC , LATORRE FERNANDO , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MEYREM , KOTSELIDIS CHRISTOS E , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
IPC分类号： G06F9/06 , G06F12/08
CPC分类号： G06F12/0815 , G06F2212/507
摘要： Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.
摘要翻译：描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的所有权投标请求（SRFOWD）。使用SRFOWD，可以仅提供确认消息作为请求内核的答案。受影响的缓存行的内容不需要作为答案的一部分。增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。如果请求的核心的猜测证明是正确的，则可以丢弃该高速缓存行的旧内容。否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。

2. 发明申请

WO2010060084A2 SYSTEMS, METHODS, AND APPARATUSES TO DECOMPOSE A SEQUENTIAL PROGRAM INTO MULTIPLE THREADS, EXECUTE SAID THREADS, AND RECONSTRUCT THE SEQUENTIAL EXECUTION 审中-公开
标题翻译：将连续程序分解为多个线程，执行线程并重新构建连续执行的系统，方法和设备
公开(公告)号：WO2010060084A2
公开(公告)日：2010-05-27
申请号：PCT/US2009065735
申请日：2009-11-24
申请人： INTEL CORP , LATORRE FERNANDO , CODINA JOSEP M , GIBERT ENRIC , LOPEZ PEDRO , MADRILES CARLOS , MARTINEZ ALEJANDRO , MARTINEZ RAUL , GONZALEZ ANTONIO
发明人： LATORRE FERNANDO , CODINA JOSEP M , GIBERT ENRIC , LOPEZ PEDRO , MADRILES CARLOS , MARTINEZ ALEJANDRO , MARTINEZ RAUL , GONZALEZ ANTONIO
IPC分类号： G06F9/30 , G06F12/00 , G06F13/00
CPC分类号： G06F9/3842 , G06F8/433 , G06F8/452 , G06F8/457 , G06F9/3851 , G06F9/3861
摘要： Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
摘要翻译：描述了用于将顺序程序分解成多个线程，执行这些线程以及重建线程的顺序执行的系统，方法和装置。多个数据高速缓存单元（DCU）存储推测执行的线程的本地退役指令。合并级别缓存（MLC）合并来自DCU的行的数据。核心间存储器一致性模块（ICMC）全局退避MLC中推测执行的线程的指令。

3. 发明申请

WO2006122990A3 STORAGE-DEPLOYMENT APPARATUS, SYSTEM AND METHOD FOR MULTIPLE SETS OF SPECULATIVE-TYPE INSTRUCTIONS 审中-公开
标题翻译：存储部署设备，多种参数类型指令的系统和方法
公开(公告)号：WO2006122990A3
公开(公告)日：2008-07-03
申请号：PCT/ES2005000279
申请日：2005-05-19
申请人： INTEL CORP , MADRILES CARLOS , RUNDBERG PETER , SANCHEZ JESUS , GARCIA CARLOS , MARCUELLO PEDRO , GONZALEZ ANTONIO
发明人： MADRILES CARLOS , RUNDBERG PETER , SANCHEZ JESUS , GARCIA CARLOS , MARCUELLO PEDRO , GONZALEZ ANTONIO
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： The invention relates to a multiversion storage configuration which can store multiple values per speculative set of instructions for one storage position in order to enable the real-time precalculation and execution of the body of the set of instructions from a speculative instruction set. The invention also relates to the validation of the input values which can be calculated and used in the execution of the speculative instruction set. The invention further relates to a method of performing said validation step.
摘要翻译：本发明涉及一种多维度存储配置，其可以为每个用于一个存储位置的每个推测的指令集存储多个值，以便能够从推测性指令集中实时预先计算和执行该组指令的正文。本发明还涉及可以在推测指令集的执行中计算和使用的输入值的验证。本发明还涉及一种执行所述验证步骤的方法。

4. 发明专利

JP2010244544A Register checkpointing mechanism for multithreading 有权
标题翻译：注册检查机制进行多元化
公开(公告)号：JP2010244544A
公开(公告)日：2010-10-28
申请号：JP2010080729
申请日：2010-03-31
申请人： Intel Corp , インテルコーポレイション
发明人： LOPEZ PEDRO , MADRILES CARLOS , MARTINEZ ALEJANDRO , MARTINEZ RAUL , CODINA JOSEPH M , CODINA ENRIC GIBERT , LATORRE FERNANDO , GONZALEZ ANTONIO
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/3863 , G06F9/30043 , G06F9/3842 , G06F9/3851 , G06F11/1402
摘要： PROBLEM TO BE SOLVED: To resolve multithreading mis-speculation.
SOLUTION: A number of multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. The threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. The threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：解决多线程错误猜测。
解决方案：多个线程单元同时执行线程。它们执行检查点掩码指令来初始化存储器以存储包括寄存器内容的活动检查点数据和指示存储的寄存器内容的有效性的检查点掩码。随着寄存器内容的改变，线程执行检查点写入指令来存储寄存器内容并更新检查点掩码。线程还执行恢复功能指令来存储指向检查点恢复功能的指针，并且响应于线程之间的错误猜测，分支到检查点恢复功能。线程然后执行一个或多个检查点读取指令以将数据从有效的检查点存储区域复制到恢复有效架构状态所需的寄存器中，从该执行可以恢复。版权所有（C）2011，JPO＆INPIT

5. 发明公开

EP2798470A4 MANAGED INSTRUCTION CACHE PREFETCHING 审中-公开
标题翻译： VERWALTETE BEFEHLSCACHESPEICHER-VORABLADUNG
公开(公告)号：EP2798470A4
公开(公告)日：2015-07-15
申请号：EP11878987
申请日：2011-12-29
申请人： INTEL CORP
发明人： STAVROU KYRIAKOS A , GIBERT CODINA ENRIC , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MIREM , KOTSELIDIS CHRISTOS E , LATORRE FERNANDO , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/3017 , G06F9/3802 , G06F9/3806 , G06F9/3848 , G06F12/0862 , G06F2212/452
摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
摘要翻译：公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。动态优化器可用于控制：识别公共指令高速缓存未命中，并将预取引擎的预取指令插入指令高速缓存。

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