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1. 发明专利

AT439719T 未知
公开(公告)号：AT439719T
公开(公告)日：2009-08-15
申请号：AT04756462
申请日：2004-06-29
申请人： INTEL CORP
发明人： RAGHUNANDAN MAKARAM
IPC分类号： H04L12/56 , G06F17/30
摘要： A method of generating a trie having a reduced number of trie blocks. An algorithm identifies data to be to be added to a trie. The algorithm separates the data into portions having sizes based, at least in part, on sizes related to trie blocks in the trie. The algorithm indicates in a trie entry of a first trie block, wherein a first portion of the prefix identifies the trie entry, that a second portion of the prefix is stored in a pruned-trie entry. The algorithm indicates in the trie entry of the first trie block a location of the pruned-trie entry, and stores the second portion of the prefix in the pruned-trie entry. The algorithm indicates in the pruned-trie entry the position the second portion occupies relative to other portions of the data.

2. 发明专利

GB2539748B Configuring power management functionality in a processor 未知
公开(公告)号：GB2539748B
公开(公告)日：2017-06-21
申请号：GB201603816
申请日：2013-06-27
申请人： INTEL CORP
发明人： MALINI K BHANDARU , ERIC DEHAEMER , RAGHUNANDAN MAKARAM , VIVEK GARG , SCOTT P BOBHOLZ
IPC分类号： G06F1/32
摘要： In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

3. 发明专利

GB2539747A Configuring power management functionality in a processor 未知
公开(公告)号：GB2539747A
公开(公告)日：2016-12-28
申请号：GB201603811
申请日：2013-06-27
申请人： INTEL CORP
发明人： MALINI K BHANDARU , ERIC DEHAEMER , RAGHUNANDAN MAKARAM , VIVEK GARG , SCOTT P BOBHOLZ
IPC分类号： G06F1/32
摘要： A processor with multiple cores (120-a to 120-n) to independently execute instructions. The single power domain indicator indicates whether multiple cores are treated as a single power domain to operate at a common performance state. A voltage regulator independently provides a regulated voltage to cores that enables multiple cores to be an independent power domain. A power controller causes the voltage regulator to provide a different regulated voltage to the core to operate at the independent performance state. The single power domain indicator indicates whether multiple cores are treated as a single power domain to operate at a common performance state, thus reduces the amount of logic that may be present on integrated circuit devices. The processor comprises multiple cores to independently execute instructions, thus reduces the consumption of the energy by hardware, and also reduces temperature, and hence increase overall system performance with both voltage and frequency modification. The processor maybe a system on a chip with additional voltage regulators formed on a single semiconductor die to enable different domains in the cores, or processor circuitry external to the cores.

4. 发明公开

EP2126688A4 METHOD FOR PROCESSING MULTIPLE OPERATIONS 审中-公开
标题翻译：一种用于处理多个操作
公开(公告)号：EP2126688A4
公开(公告)日：2011-06-01
申请号：EP07854971
申请日：2007-12-05
申请人： INTEL CORP
发明人： FEGHALI WAJDI , HIRNAK STEPHANIE , RAGHUNANDAN MAKARAM , BANSAL YOGESH , YAP KIRK , WOLRICH GILBERT M
IPC分类号： G06F9/06 , G06F9/38 , G06F9/46 , G06F12/08
CPC分类号： H04L63/0485 , G06F9/3879 , G06F9/3885 , H04L63/08
摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

5. 发明专利

GB2539749A Configuring power management functionality in a processor 未知
公开(公告)号：GB2539749A
公开(公告)日：2016-12-28
申请号：GB201603821
申请日：2013-06-27
申请人： INTEL CORP
发明人： MALINI K BHANDARU , ERIC DEHAEMER , RAGHUNANDAN MAKARAM , VIVEK GARG , SCOTT P BOBHOLZ
IPC分类号： G06F1/32
摘要： A processor with multiple cores (120-a to 120-n) to independently execute instructions. The single power domain indicator indicates whether multiple cores are treated as a single power domain to operate at a common performance state. A voltage regulator independently provides a regulated voltage to cores that enables multiple cores to be an independent power domain. A power controller causes the voltage regulator to provide a different regulated voltage to the core to operate at the independent performance state. The single power domain indicator indicates whether multiple cores are treated as a single power domain to operate at a common performance state, thus reduces the amount of logic that may be present on integrated circuit devices. The processor comprises multiple cores to independently execute instructions, thus reduces the consumption of the energy by hardware, and also reduces temperature, and hence increase overall system performance with both voltage and frequency modification. The processor maybe a system on a chip with additional voltage regulators formed on a single semiconductor die to enable different domains in the cores, or processor circuitry external to the cores.

6. 发明专利

GB2539748A Configuring power management functionality in a processor 未知
公开(公告)号：GB2539748A
公开(公告)日：2016-12-28
申请号：GB201603816
申请日：2013-06-27
申请人： INTEL CORP
发明人： MALINI K BHANDARU , ERIC DEHAEMER , RAGHUNANDAN MAKARAM , VIVEK GARG , SCOTT P BOBHOLZ
IPC分类号： G06F1/32
摘要： A processor with multiple cores (120-a to 120-n) to independently execute instructions. The single power domain indicator indicates whether multiple cores are treated as a single power domain to operate at a common performance state. A voltage regulator independently provides a regulated voltage to cores that enables multiple cores to be an independent power domain. A power controller causes the voltage regulator to provide a different regulated voltage to the core to operate at the independent performance state. The single power domain indicator indicates whether multiple cores are treated as a single power domain to operate at a common performance state, thus reduces the amount of logic that may be present on integrated circuit devices. The processor comprises multiple cores to independently execute instructions, thus reduces the consumption of the energy by hardware, and also reduces temperature, and hence increase overall system performance with both voltage and frequency modification. The processor maybe a system on a chip with additional voltage regulators formed on a single semiconductor die to enable different domains in the cores, or processor circuitry external to the cores.

7. 发明专利

ES2805125T3 Arquitectura e instrucciones flexibles para el estándar de cifrado avanzado (AES) 未知
公开(公告)号：ES2805125T3
公开(公告)日：2021-02-10
申请号：ES18165550
申请日：2008-03-25
申请人： INTEL CORP
发明人： GUERON SHAY , FEGHALI WAJDI , GOPAL VINODH , RAGHUNANDAN MAKARAM , DIXON MARTIN , CHENNUPATY SRINIVAS , KOUNAVIS MICHAEL
IPC分类号： H04L9/06 , G06F3/06 , G06F9/30 , G06F9/38 , G06F12/0862 , G06F12/0875 , G06F12/14 , G06F21/60 , G11C7/10 , H04L9/08
摘要： Un procesador que comprende: una pluralidad de núcleos; una caché de instrucciones de nivel 1, L1, para almacenar una pluralidad de instrucciones del estándar de cifrado avanzado, AES, cada instrucción AES tiene un opcode único; una caché de datos de L1; lógica de extracción de instrucciones para extraer instrucciones de la caché de instrucciones de L1; lógica de decodificación para decodificar las instrucciones; un primer registro de origen para almacenar una clave de ciclo a ser utilizada para un ciclo de una operación de cifrado AES; un segundo registro de origen para almacenar datos de entrada a ser cifrados mediante el ciclo de la operación de cifrado AES; y una unidad de ejecución que incluye lógica de ejecución AES para ejecutar al menos una primera instrucción AES de la pluralidad de instrucciones AES para realizar el ciclo de la operación de cifrado AES, el ciclo de la operación de cifrado AES que utiliza la clave de ciclo del primer registro de origen para cifrar los datos de entrada del segundo registro de origen y almacena un resultado del ciclo de la operación de cifrado AES en un primer registro de destino.

8. 发明专利

GB2539749B Configuring power management functionality in a processor 未知
公开(公告)号：GB2539749B
公开(公告)日：2017-06-21
申请号：GB201603821
申请日：2013-06-27
申请人： INTEL CORP
发明人： MALINI K BHANDARU , ERIC DEHAEMER , RAGHUNANDAN MAKARAM , VIVEK GARG , SCOTT P BOBHOLZ
IPC分类号： G06F1/32
摘要： In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

9. 发明专利

SG146584A1 FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) 未知
公开(公告)号：SG146584A1
公开(公告)日：2008-10-30
申请号：SG2008023830
申请日：2008-03-26
申请人： INTEL CORP
发明人： SHAY GUERON K , FEGHALI WAJDI , GOPAL VINODH , RAGHUNANDAN MAKARAM , DIXON MARTIN G , CHENNUPATY SRINIVAS , KOUNAVIS MICHAEL E
摘要： FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

10. 发明专利

GB2539747B Configuring power management functionality in a processor 未知
公开(公告)号：GB2539747B
公开(公告)日：2017-06-21
申请号：GB201603811
申请日：2013-06-27
申请人： INTEL CORP
发明人： MALINI K BHANDARU , ERIC DEHAEMER , RAGHUNANDAN MAKARAM , VIVEK GARG , SCOTT P BOBHOLZ
IPC分类号： G06F1/32
摘要： In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

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