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1. 发明专利

AU2002352948A1 AUTOMATIC MONITORING OF HOST SIGNAL QUALITY USING EMBEDDED DATA 未知
公开(公告)号：AU2002352948A1
公开(公告)日：2003-07-09
申请号：AU2002352948
申请日：2002-11-26
申请人： INTEL CORP
发明人： HOLLIMAN MATTHEW , YEUNG MINERVA
IPC分类号： G06T1/00 , H04N17/00 , H04N19/89 , H04N19/895 , H04N21/2389 , H04N21/2543 , H04N21/442 , H04N21/8358 , H04N7/24

2. 发明申请

WO2004034265A2 AN APPARATUS AND METHOD FOR FACILITATING MEMORY DATA ACCESS WITH GENERIC READ/WRITE PATTERNS 审中-公开
标题翻译：用于通用读/写模式来提高存储器数据访问的装置和方法
公开(公告)号：WO2004034265A2
公开(公告)日：2004-04-22
申请号：PCT/US0330578
申请日：2003-09-26
申请人： INTEL CORP
发明人： CHEN YEN-KUANG , DEBES ERIC , HOLLIMAN MATTHEW , YEUNG MINERVA
IPC分类号： G06F12/08 , G06T1/60 , G06T9/00 , G09G5/393 , G06F12/02 , G06F9/38 , G06T1/20
CPC分类号： G06F12/0875 , G06F12/0877 , G06T1/60 , G06T9/00 , G09G5/393 , G09G2360/121
摘要： An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.
摘要翻译：描述了利用通用读/写模式促进存储器数据访问的装置和方法。在一个实施例中，该方法包括响应于加载指令，检测在重新平铺（RT）高速缓存内由加载指令请求的数据的高速缓存命中/高速缓存未命中。当检测到高速缓存未命中时，根据加载指令将一块数据加载到RT缓存中。该数据块将包含加载指令请求的数据。一旦加载，从RT缓存执行加载指令请求的数据的非水平顺序访问。最后，从RT缓存访问的数据可以根据加载指令存储到目的地数据存储装置中。

3. 发明专利

AT464597T 未知
公开(公告)号：AT464597T
公开(公告)日：2010-04-15
申请号：AT02798099
申请日：2002-08-30
申请人： INTEL CORP
发明人： MACY WILLIAM , HOLLIMAN MATTHEW , DEBES ERIC , CHEN YEN-KUANG
IPC分类号： G06F5/06 , G06F9/34 , G06F1/00 , G06F5/01 , G06F9/305 , G06F9/38 , G06F12/04 , H03M7/30
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.

4. 发明申请

WO2004034263A3 PERFORMING VIDEO/IMAGE DATA ACCESS IN ACCORDANCE WTH MEMORY ACCESS PATTERN: MPEG-4, JPEG2000 STREAMING SIMD EXTENSIONS 审中-公开
标题翻译：根据视频/图像数据访问WTH存储器访问模式：MPEG-4，JPEG2000流水线SIMD扩展
公开(公告)号：WO2004034263A3
公开(公告)日：2005-11-24
申请号：PCT/US0330572
申请日：2003-09-26
申请人： INTEL CORP
发明人： DEBES ERIC , CHEN YEN-KUANG , HOLLIMAN MATTHEW , YEUNG MINERVA
IPC分类号： G06F12/08 , G06T1/60 , G09G5/393 , G06F9/345 , G06T1/20
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0897 , G06T1/60 , G09G5/393
摘要： An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.
摘要翻译：描述了根据存储器访问模式执行数据访问的装置和方法。在一个实施例中，该方法包括响应于存储器访问指令确定由存储器访问指令请求的数据的存储器访问模式。一旦确定了存储器访问模式，则根据所确定的存储器访问模式访问由存储器访问指令请求的数据。最后，访问数据后，根据存储器访问指令对数据进行处理。因此，在本发明的这个实施例中，根据存储器访问模式访问数据，包括锯齿形图案扫描，Zerotree扫描，位平面提取，细粒度可伸缩性等。

5. 发明申请

WO03023600A2 AN APPARATUS AND METHOD FOR EXTRACTING AND LOADING DATA TO/FROM A BUFFER 审中-公开
标题翻译：一种用于从缓冲器提取和加载数据的装置和方法
公开(公告)号：WO03023600A2
公开(公告)日：2003-03-20
申请号：PCT/US0227725
申请日：2002-08-30
申请人： INTEL CORP
发明人： MACY WILLIAM JR , HOLLIMAN MATTHEW , DEBES ERIC , CHEN YEN-KUANG
IPC分类号： G06F9/34 , G06F1/00 , G06F5/01 , G06F5/06 , G06F9/305 , G06F9/38 , G06F12/04 , H03M7/30
CPC分类号： G06F5/065
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit- level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
摘要翻译：描述了一种用于提取和从缓冲器加载数据的装置和方法。该方法包括响应于数据访问指令的执行从数据缓冲器中选择数据。数据缓冲器包括多个数据存储设备，其中一个或多个初始地包含所选择的数据。因此，多个数据存储装置形成在位层可寻址的单个地址空间。当所选择的数据从源数据存储装置跨越到数据缓冲器的下一个数据存储装置时，来自源数据存储装置的所选数据的一部分与来自下一数据存储装置的所选数据的剩余部分相连，将所选数据形成为连续单位。最后，一旦形成所选择的数据，所选择的数据被存储在目的地数据存储装置中。

6. 发明专利

AU2003272756A1 AN APPARATUS AND METHOD FOR FACILITATING MEMORY DATA ACCESS WITH GENERIC READ/WRITE PATTERNS 未知
公开(公告)号：AU2003272756A1
公开(公告)日：2004-05-04
申请号：AU2003272756
申请日：2003-09-26
申请人： INTEL CORP
发明人： DEBES ERIC , HOLLIMAN MATTHEW , YEUNG MINERVA , CHEN YEN-KUANG
IPC分类号： G06F12/08 , G06T1/60 , G06T9/00 , G09G5/393 , G06F12/02 , G06T1/20 , G06F9/38
摘要： An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.

7. 发明专利

AU2003217255A1 METHOD AND APPARATUS FOR VARIABLE LENGTH CODING OF BIT PLANES 未知
公开(公告)号：AU2003217255A1
公开(公告)日：2003-09-02
申请号：AU2003217255
申请日：2003-01-24
申请人： INTEL CORP
发明人： HAMMARLUND PER , HUFF THOMAS , MACY WILLIAM JR , CHEN YEN-KUANG , HOLLIMAN MATTHEW , HUM HERBERT
IPC分类号： G11B20/14 , H03M5/14 , H03M7/40 , H03M7/46 , H04N7/26 , H04N1/41 , G06F9/38
摘要： A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

8. 发明专利

DE60236000D1 未知
公开(公告)号：DE60236000D1
公开(公告)日：2010-05-27
申请号：DE60236000
申请日：2002-08-30
申请人： INTEL CORP
发明人： MACY WILLIAM JR , HOLLIMAN MATTHEW , DEBES ERIC , CHEN YEN-KUANG
IPC分类号： G06F5/06 , G06F9/34 , G06F1/00 , G06F5/01 , G06F9/305 , G06F9/38 , G06F12/04 , H03M7/30
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.

9. 发明专利

AU2003272756A8 An apparatus and method for facilitating memory data access with generic read/write patterns 未知
公开(公告)号：AU2003272756A8
公开(公告)日：2004-05-04
申请号：AU2003272756
申请日：2003-09-26
申请人： INTEL CORP
发明人： YEUNG MINERVA , DEBES ERIC , HOLLIMAN MATTHEW , CHEN YEN-KUANG
IPC分类号： G06F12/08 , G06T1/60 , G06T9/00 , G09G5/393 , G06F9/38 , H04N7/50 , G06F9/318
摘要： An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.

10. 发明专利

AU2003272753A1 AN APPARATUS AND METHOD FOR PERFORMING DATA ACCESS IN ACCORDANCE WITH MEMORY ACCESS PATTERNS 未知
公开(公告)号：AU2003272753A1
公开(公告)日：2004-05-04
申请号：AU2003272753
申请日：2003-09-26
申请人： INTEL CORP
发明人： DEBES ERIC , CHEN YEN-KUANG , HOLLIMAN MATTHEW , YEUNG MINERVA
IPC分类号： G06F12/08 , G06T1/60 , G09G5/393 , G06F12/00
摘要： An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

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