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1. 发明申请

WO2014051741A3 INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS 审中-公开
标题翻译：集成电路具有可访问且不可访问的物理无可比拟的功能
公开(公告)号：WO2014051741A3
公开(公告)日：2014-09-12
申请号：PCT/US2013045517
申请日：2013-06-12
申请人： INTEL CORP
发明人： GOTZE KEVIN C , IOVINO GREGORY M , LI JIANGTAO , JOHNSTON DAVID , MATHEW SANU K , COX GEORGE W , RAJAN ANAND
IPC分类号： G06F21/00
CPC分类号： H03K19/003 , G09C1/00 , H04L9/0866 , H04L2209/12
摘要： An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.
摘要翻译：一方面的集成电路衬底包括多个暴露的电触点。集成电路衬底还包括不可访问的一组物理不可复制功能（PUF）单元，以生成不可通过暴露的电触点访问的不可访问的一组PUF位。集成电路衬底还包括可访问的一组PUF单元以生成可通过暴露的电触点访问的可访问的一组PUF位。其他装置，方法和系统也被公开。

2. 发明专利

DE3072127D1 DATA PROCESSING SYSTEM 未知
公开(公告)号：DE3072127D1
公开(公告)日：1988-12-08
申请号：DE3072127
申请日：1980-02-28
申请人： INTEL CORP
发明人： COLLEY STEPHEN R , COX GEORGE W , RATTNER JUSTIN R , SWANSON ROGER C
IPC分类号： G06F9/46 , F02B75/02 , G06F9/318 , G06F9/50 , G06F12/10 , G06F12/1036 , G06F12/1045 , G06F12/14 , G06F15/16

3. 发明专利

AU4658597A Object-based digital signatures 未知
公开(公告)号：AU4658597A
公开(公告)日：1998-05-29
申请号：AU4658597
申请日：1997-09-29
申请人： INTEL CORP
发明人： COX GEORGE W , AUCSMITH DAVID W , ONNEN PAUL E
IPC分类号： H04L9/32 , H04L9/30
摘要： Briefly, in accordance with one embodiment of the invention, a method of using a digital signature includes: electronically referencing at least one plurality of electronic signals with a digital signature remotely stored from the plurality.

4. 发明公开

EP2798771A4 METHOD AND APPARATUS FOR A NON-DETERMINISTIC RANDOM BIT GENERATOR (NRBG) 审中-公开
标题翻译：方法和装置的非确定性随机位发生器
公开(公告)号：EP2798771A4
公开(公告)日：2015-10-07
申请号：EP11878687
申请日：2011-12-29
申请人： INTEL CORP
发明人： COX GEORGE W , JOHNSTON DAVID , DIXON MARTIN G , FISCHER STEPHEN A , BRANDT JASON W
IPC分类号： H04L9/22 , G06F7/58 , G06F9/30 , H04L9/06 , H04L9/08
CPC分类号： H04L9/0869 , G06F7/588 , G06F9/30007 , H04L9/0662 , H04L2209/24

5. 发明专利

DE112013005431T5 Sichere Schlüsselableitungs- und Kryptografielogik für integrierte Schaltungen 未知
公开(公告)号：DE112013005431T5
公开(公告)日：2015-07-30
申请号：DE112013005431
申请日：2013-06-19
申请人： INTEL CORP
发明人： COX GEORGE W , JOHNSTON DAVID , RAJAN ANAND , LI JIANGTAO
IPC分类号： G06F21/73
摘要： Ein Prozessor eines Aspekts enthält Stammschlüssel-Generierungslogik, um einen Stammschlüssel zu generieren. Die Stammschlüssel-Generierungslogik enthält eine Quelle für statische und entropische Bits. Der Prozessor enthält auch Schlüsselableitungslogik, die mit der Stammschlüssel-Generierungslogik verkoppelt ist. Die Schlüsselableitungslogik dient zum Ableiten eines oder mehrerer Schlüssel aus dem Stammschlüssel. Der Prozessor enthält auch kryptografische primitive Logik, die mit der Stammschlüssel-Generierungslogik verkoppelt ist. Die kryptografische primitive Logik dient zum Durchführen kryptografischer Operationen. Der Prozessor enthält auch eine Sicherheitsgrenze, die die Stammschlüssel-Generierungslogik, die Schlüsselableitungslogik und die kryptografische primitive Logik umfasst. Andere Prozessoren, Verfahren und Systeme werden ebenfalls offenbart.

6. 发明专利

AT38442T 未知
公开(公告)号：AT38442T
公开(公告)日：1988-11-15
申请号：AT80901676
申请日：1980-02-28
申请人： INTEL CORP
发明人： COLLEY STEPHEN R , COX GEORGE W , RATTNER JUSTIN R , SWANSON ROGER C
IPC分类号： G06F9/46 , F02B75/02 , G06F9/318 , G06F9/50 , G06F12/10 , G06F12/1036 , G06F12/1045 , G06F12/14 , G06F15/16

7. 发明专利

GB2520196A Integrated circuits having accessible and inaccessible physically unclonable functions 未知
公开(公告)号：GB2520196A
公开(公告)日：2015-05-13
申请号：GB201500820
申请日：2013-06-12
申请人： INTEL CORP
发明人： GOTZE KEVIN C , IOVINO GREGORY M , LI JIANGTAO , JOHNSTON DAVID , MATHEW SANU K , COX GEORGE W , RAJAN ANAND
IPC分类号： H01L21/66 , G06F21/72 , H04L9/08
摘要： An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.

8. 发明公开

EP2877955A4 PROVIDING ACCESS TO ENCRYPTED DATA 有权
标题翻译：提供访问加密数据
公开(公告)号：EP2877955A4
公开(公告)日：2016-03-16
申请号：EP13822709
申请日：2013-07-18
申请人： INTEL CORP
发明人： SMITH NED M , COX GEORGE W , JOHNSTON DAVID
IPC分类号： G06F21/30 , G06F12/14 , G06F21/31 , G06F21/60 , G06F21/62 , G06F21/74 , H04L9/08 , H04L9/32
CPC分类号： H04L9/0866 , G06F21/31 , G06F21/6209 , G06F21/74 , G06F2221/2107 , H04L9/0822 , H04L9/3226
摘要： Embodiments of methods, systems, and storage medium associated with providing access to encrypted data for authorized users are disclosed herein. In one instance, the method may include obtaining a derived value for an authenticated user based on user personalization data of the authenticated user, and generating a user-specific encryption key based on the derived value. The derived value may have entropy in excess of a predetermined level. The user-specific encryption key may enable the authenticated user to access the encrypted data stored at the storage device. Other embodiments may be described and/or claimed.

9. 发明公开

EP0938792A4 OBJECT-BASED DIGITAL SIGNATURES 失效
标题翻译：面向对象的数字签名
公开(公告)号：EP0938792A4
公开(公告)日：2001-08-29
申请号：EP97945363
申请日：1997-09-29
申请人： INTEL CORP
发明人： COX GEORGE W , AUCSMITH DAVID W , ONNEN PAUL E
IPC分类号： H04L9/32 , H04L9/30
CPC分类号： H04L9/3247 , H04L9/3263
摘要： Briefly, in accordance with one embodiment of the invention, a method of using a digital signature (110) comprises a step of: electronically referencing at least one plurality of electronic signals (125) with a digital signature remotely stored from the plurality.

10. 发明公开

EP0047238A4 DATA PROCESSING SYSTEM. 失效
标题翻译： DATENVERARBEITUNGSSYSTEM。
公开(公告)号：EP0047238A4
公开(公告)日：1986-08-21
申请号：EP80901676
申请日：1980-02-28
申请人： INTEL CORP
发明人： COLLEY STEPHEN R , COX GEORGE W , RATTNER JUSTIN R , SWANSON ROGER C
IPC分类号： G06F9/46 , F02B75/02 , G06F9/318 , G06F9/50 , G06F12/10 , G06F12/14 , G06F15/16 , G06F3/00 , G06F7/00 , G06F9/00 , G06F13/00 , G06F15/20
CPC分类号： G06F12/1483 , F02B2075/027 , G06F9/30192 , G06F9/468 , G06F9/4881 , G06F12/1036 , G06F12/109 , G06F2209/483
摘要： A data processor architecture wherein the processors recognize two basic types of objects, an object being a representation of related information maintained in a contiguously addressed set of memory locations. The first type of object contains ordinary data, such as characters, integers, reals, etc. The second type of object contains a list of access descriptors. Each access descriptor provides information for locating and defining the extent of access to an object associated with that access descriptor. The processors recognize complex objects that are combinations of objects of the basic types. One such complex object (94) defines an environment (18 or 20) for execution of objects (92, 93, 98, 106, 122) accessible to a given instance of a procedural operation. The dispatching of tasks to the processor is accomplished by hardware-controlled queuing mechanisms (36), dispatching-port objects (146) which allow multiple sets of processors (38) and (40) to serve multiple, but independent sets of tasks (14, 16). Communication between asychronous tasks or processes is accomplished by related hardware controlled queuing mechanisms (34) (buffered-port objects) (144) which allow messages to move between internal processes or input/output processes without the need for interrupts. A mechanism (42) is provided which allows the processors to communicate with each other. This mechanism is used to reawaken an idle processor to alert the processor to the fact that a ready-to-run process at a dispatching port needs execution.
摘要翻译：一种数据处理器架构，其中处理器识别两种基本类型的对象，一种对象是在连续寻址的一组存储器位置中保存的相关信息的表示。第一类对象包含普通数据，如字符，整数，实数等。第二类对象包含访问描述符列表。每个访问描述符提供用于定位和定义访问与访问描述符相关联的对象的范围的信息。处理器识别作为基本类型的对象的组合的复杂对象。一个这样的复杂对象（94）定义了用于执行可供程序操作的给定实例访问的对象（92,93,98,106,122）的环境（18或20）。通过硬件控制的排队机制（36），允许多组处理器（38）和（40）为多个但独立的任务组（14）提供服务的调度端口对象（146）来完成向处理器分派任务。，16）。异步任务或进程之间的通信由相关的硬件控制的排队机制（34）（缓冲端口对象）（144）来完成，其允许消息在内部进程或输入/输出进程之间移动而不需要中断。提供了允许处理器相互通信的机制（42）。这种机制用于唤醒处理器，以唤醒处理器，指出调度端口上的准备就绪进程需要执行。

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