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1. 发明申请

US20160172495A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20160172495A1
公开(公告)日：2016-06-16
申请号：US14439179
申请日：2012-11-27
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong ZHU , Haizhou YIN , Zhijiong LUO
IPC分类号： H01L29/78 , H01L21/308 , H01L29/08 , H01L29/06 , H01L21/02 , H01L21/027 , H01L29/417 , H01L29/161 , H01L29/165 , H01L29/16 , H01L29/66 , H01L21/762
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/0274 , H01L21/308 , H01L21/76224 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/0653 , H01L29/0688 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located above the base region (100), and the base region (100) is supported above the substrate (130) by the support structure (131), wherein the support structure (131) has a sigma-shaped lateral cross-section; an isolation structure (123) is formed below edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and a source/drain region is formed on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also provided.
摘要翻译：提供了一种半导体结构，包括基板（130），支撑结构（131），基极区（100），栅极叠层，间隔物（240）和源极/漏极区，其中栅极堆叠位于在所述基部区域（100）上方，并且所述基部区域（100）由所述支撑结构（131）支撑在所述基板（130）上方，其中所述支撑结构（131）具有σ形横截面; 在基底区域（100）的两侧的边缘下方形成隔离结构（123），其中隔离结构（123）的一部分连接到基底（130）; 在隔离结构（123）和支撑结构（131）之间形成空腔（112）; 并且在基极区域（100）和隔离结构（123）的两侧形成源极/漏极区域。因此，还提供了一种用于制造半导体结构的方法。

2. 发明申请

US20150380297A1 METHOD FOR MANUFACTURING MOSFET 审中-公开
标题翻译：制造MOSFET的方法
公开(公告)号：US20150380297A1
公开(公告)日：2015-12-31
申请号：US14759324
申请日：2012-10-30
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou YIN , Changliang QIN , Huilong ZHU
IPC分类号： H01L21/762 , H01L21/311 , H01L29/16 , H01L29/06 , H01L29/66
CPC分类号： H01L21/76232 , H01L21/31144 , H01L21/76283 , H01L29/045 , H01L29/0657 , H01L29/1608 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Provided is a method for manufacturing a MOSFET, comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a shallow trench isolation in the first semiconductor layer and the second semiconductor layer to define an active region for the MOSFET; forming on the second semiconductor layer a gate stack and a spacer surrounding the gate stack; forming openings in the second semiconductor layer using the shallow trench isolation, the gate stack and the spacer as a hard mask; epitaxially growing, in each of the openings, a third semiconductor layer using a bottom surface and sidewalls of the opening as a growth seed layer, wherein the third semiconductor layer comprises a material different from that of the second semiconductor layer; and performing ion implantation into the third semiconductor layer to form source and drain regions.
摘要翻译：提供一种用于制造MOSFET的方法，包括：在半导体衬底上外延生长第一半导体层; 在所述第一半导体层上外延生长第二半导体层; 在所述第一半导体层和所述第二半导体层中形成浅沟槽隔离以限定所述MOSFET的有源区; 在所述第二半导体层上形成栅极堆叠和围绕所述栅极叠层的间隔区; 使用浅沟槽隔离在第二半导体层中形成开口，栅极堆叠和间隔物作为硬掩模; 在每个开口中外延生长使用底表面和开口侧壁作为生长种子层的第三半导体层，其中第三半导体层包括与第二半导体层不同的材料; 以及对所述第三半导体层进行离子注入以形成源区和漏区。

3. 发明申请

US20150340456A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150340456A1
公开(公告)日：2015-11-26
申请号：US14412173
申请日：2012-07-19
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou YIN , Huilong ZHU , Keke ZHANG
IPC分类号： H01L29/423 , H01L29/78 , H01L21/3105 , H01L21/28 , H01L29/66
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/31051 , H01L29/41783 , H01L29/42376 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

4. 发明申请

US20160172446A1 MOSFET STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译： MOSFET结构及其制造方法
公开(公告)号：US20160172446A1
公开(公告)日：2016-06-16
申请号：US14905440
申请日：2013-10-22
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou YIN
IPC分类号： H01L29/10 , H01L29/78 , H01L29/08 , H01L21/02 , H01L21/308 , H01L29/165 , H01L29/66
CPC分类号： H01L29/1054 , H01L21/02532 , H01L21/308 , H01L21/8234 , H01L21/823412 , H01L29/0847 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/78 , H01L29/7833
摘要： A MOSFET and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100), a dummy gate structure (200), a epitaxial protection layer (101) and a sacrificial spacer (205); b. covering the dummy gate structure (200) and the substrate (100) on one side thereof by a mask layer, and forming a vacancy (102) in the substrate; c. growing a semiconductor layer (300) on the semiconductor structure to fill in the vacancy (102); d. removing the epitaxial protection layer (101) and the sacrificial spacer (205), and sequentially forming source/drain extension regions, a spacer (201), source/drain regions, and an interlayer dielectric layer (500); and e. removing the dummy gate structure (200) to form a dummy gate vacancy, and forming a gate stack in the dummy gate vacancy. In the MOSFET structure of the present disclosure, negative effects of DIBL on device performance can be effectively reduced.
摘要翻译：公开了一种MOSFET及其制造方法。该方法包括：a。提供衬底（100），伪栅极结构（200），外延保护层（101）和牺牲间隔物（205）; b。通过掩模层在其一侧覆盖伪栅极结构（200）和衬底（100），并在衬底中形成空位（102）; C。在半导体结构上生长半导体层（300）以填充空位（102）; d。去除外延保护层（101）和牺牲间隔物（205），顺序地形成源极/漏极延伸区域，间隔物（201），源极/漏极区域和层间介电层（500）; 和e。去除伪栅极结构（200）以形成虚拟栅极空位，以及在虚拟栅极空位中形成栅极堆叠。在本公开的MOSFET结构中，可以有效地降低DIBL对器件性能的负面影响。

5. 发明申请

US20160163832A1 FINFET AND METHOD OF MANUFACTURING SAME 有权
标题翻译： FINFET及其制造方法
公开(公告)号：US20160163832A1
公开(公告)日：2016-06-09
申请号：US14904140
申请日：2013-10-22
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou YIN , Yunfei LIU
IPC分类号： H01L29/66 , H01L29/78 , H01L21/311 , H01L21/02 , H01L29/06 , H01L21/762
CPC分类号： H01L29/66795 , H01L21/02164 , H01L21/0217 , H01L21/31116 , H01L21/76224 , H01L29/0649 , H01L29/6653 , H01L29/66545 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要： There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l. planarizing the semiconductor structure formed by the foregoing steps to expose the channel protective layer and forming a first separated gate stack and a second separated gate stack. Comparing with the prior art, control ability of independent-gate-voltage FinFET can be effectively improved and it is good for device performance.
摘要翻译：提供了一种FinFET制造方法，包括：a。提供衬底; b。在基板上形成翅片; C。在翅片上形成通道保护层; d。在鳍的两侧形成浅沟槽隔离; e。在鳍的中间的沟道区的顶表面和侧壁上形成牺牲栅叠层和间隔物; F。在鳍的两端形成源/漏区; G。在所述牺牲栅极堆叠和所述源极/漏极区域上沉积层间电介质层，以稍后平坦化以暴露所述牺牲栅极堆叠; H。去除牺牲栅极堆叠堆叠以形成牺牲栅极空位并暴露沟道区域和沟道保护层; 一世。用光致抗蚀剂层覆盖鳍的一端中的半导体结构的一部分; j。去除未覆盖的间隔件的一部分; k。去除光致抗蚀剂层并在牺牲栅极空位中填充栅极堆叠; l。平面化由上述步骤形成的半导体结构以暴露沟道保护层并形成第一分离的栅极堆叠和第二分离栅极堆叠。与现有技术相比，可以有效提高独立栅极电压FinFET的控制能力，对器件性能有好处。

6. 发明申请

US20160155844A1 ASYMMETRIC ULTRATHIN SOI MOS TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：非对称超导SOI MOS晶体管结构及其制造方法
公开(公告)号：US20160155844A1
公开(公告)日：2016-06-02
申请号：US14904711
申请日：2013-10-21
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou YIN , Keke ZHANG
IPC分类号： H01L29/78 , H01L29/06 , H01L21/02 , H01L21/265 , H01L21/306 , H01L29/66 , H01L29/08
CPC分类号： H01L29/7835 , H01L21/02636 , H01L21/26513 , H01L21/30604 , H01L29/0649 , H01L29/0847 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78603 , H01L29/78696
摘要： A method for manufacturing an asymmetric super-thin SOIMOS transistor is disclosed. The method comprises: a. providing a substrate composed of an insulating layer (200) and a semiconductor layer (300); b. forming a gate stack (304) on the substrate; c. removing semiconductor materials of the semiconductor layer (300) on a source region side to form a first vacancy (001); d. removing insulating materials of the insulating layer (200) in the source region and under channel near the source region to form a second vacancy (002); e. filling semiconductor materials into the first vacancy (001) and the second vacancy (002) to connect with the semiconductor materials above the second vacancy (002); and f. performing source/drain implantation. Compared with the prior art, the method of the disclosure can suppress the short channel effects and enhance device performance.
摘要翻译：公开了一种用于制造不对称超薄SOIMOS晶体管的方法。该方法包括：a。提供由绝缘层（200）和半导体层（300）组成的基板; b。在所述基板上形成栅叠层（304）; C。去除源区域侧的半导体层（300）的半导体材料以形成第一空位（001）; d。去除所述源极区域中的所述绝缘层（200）的绝缘材料，以及在所述源极区域附近的通道以形成第二空位（002）; e。将半导体材料填充到第一空位（001）和第二空位（002）中以与第二空位（002）之上的半导体材料连接; 和f。进行源/漏植入。与现有技术相比，本发明的方法可以抑制短信道效应并增强设备性能。

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