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1. 发明申请

WO0198836A3 METHOD OF REDUCING POST-DEVELOPMENT DEFECTS IN AND AROUND OPENINGS FORMED IN PHOTORESIST BY USE OF NON-PATTERNED EXPOSURE 审中-公开
标题翻译：通过使用非图形化曝光减少光电子体中形成的开放后期发育缺陷的方法
公开(公告)号：WO0198836A3
公开(公告)日：2002-04-18
申请号：PCT/US0119814
申请日：2001-06-21
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： LU ZHIJIAN , THOMAS ALAN , GUTMANN ALOIS , CHEN KUANG JUNG , LAWSON MARGARET
IPC分类号： G03F7/20 , H01L21/027 , G03F7/09
CPC分类号： H01L21/0274 , G03F7/2022 , G03F7/2037 , G03F7/2039 , Y10S430/168
摘要： In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable pieces of components of the photoresist material, Blob Defects, remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of introducing a low level uniform flood exposure of light in addition to the commonly used exposure to patterned light, followed by standard development. The flood exposure is in the range of 5 to 50 % of the dose-to-clear for a non-patterned exposure.
摘要翻译：在可用的深紫外（DUV）敏感光刻胶的曝光和显影中，已经观察到遵循现有技术的标准曝光和显影方法导致光致抗蚀剂材料的不希望的部件的高密度，残留在半导体衬底（主体）。曝光和显影光致抗蚀剂材料的方法导致这些斑点缺陷的发生率降低，除了通常使用的图案光曝光之外，还引入低等级的均匀泛光曝光，随后进行标准开发。对于非图案化曝光，洪水暴露在5至50％的剂量清除范围内。

2. 发明申请

WO0199186A3 SHIELDING OF ANALOG CIRCUITS ON SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：半导体衬底上模拟电路的屏蔽
公开(公告)号：WO0199186A3
公开(公告)日：2002-10-10
申请号：PCT/US0119658
申请日：2001-06-20
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： KUNKEL GERHARD , KOTECKI DAVID , PARK YOUNG JIN , GUTMANN ALOIS , MANDELMAN JACK A
IPC分类号： H01L21/761 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/761
摘要： A semiconductor device, in accordance with the present invention, includes a doped semiconductor substrate (102) wherein the doping of the substrate has a first conductivity and a device region (110) formed near a surface of the substrate. The device region includes at least one device well. A buried well (104) is formed in the substrate below the device region. The buried well is doped with dopants having a second conductivity. A trench region (124) surrounds the device region and extends below the surface of the substrate to at least the buried well such that the device region is isolated from other portions of the substrate by the buried well and the trench region.
摘要翻译：根据本发明的半导体器件包括其中衬底的掺杂具有第一导电性的掺杂半导体衬底（102）和形成在衬底的表面附近的器件区（110）。器件区域包括至少一个器件。掩埋阱（104）形成在器件区域下方的衬底中。掩埋阱掺杂具有第二导电性的掺杂剂。沟槽区域（124）围绕器件区域并且在衬底的表面下方延伸到至少掩埋阱，使得器件区域通过掩埋阱和沟槽区域与衬底的其他部分隔离。

3. 发明申请

WO0197284A3 Method for forming dual damascene structure 审中-公开
标题翻译：形成双镶嵌结构的方法
公开(公告)号：WO0197284A3
公开(公告)日：2002-04-25
申请号：PCT/US0119001
申请日：2001-06-13
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： AMRACOST MICHAEL , SPULER BRUNO , BRASE GABRIELA , GUTMANN ALOIS
IPC分类号： H01L21/768
CPC分类号： H01L21/76808
摘要： A method is provided for forming a step in a layer of material (16). The method includes forming the layer over a substrate. A cavity (24) is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material (26) to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture (30) is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion (32) of the filler material is removed along with a contiguous portion of the layer (16) to form the step in the indentation. The cavity may be either a trench or a via. A 'Trench First' approach and a 'Via First' approach are described.
摘要翻译：提供了一种用于在材料层中形成台阶的方法。该方法包括在衬底上形成该层。在该层的上表面的一部分中形成空腔。形成的空腔填充有填充材料，以在衬底上提供基本平坦的表面。光致抗蚀剂层形成在衬底上的基本平坦的表面上。光致抗蚀剂层中形成有与形成的空腔对准的孔。孔径暴露了填充材料的一部分。填充材料的暴露部分与层的连续部分一起被去除以形成凹陷中的台阶。空腔可以是沟槽或通孔。描述了“首先采取沟通”方式和“首选”方式。

4. 发明申请

WO0199161A2 METHOD OF REDUCING POST-DEVELOPMENT DEFECTS IN AND AROUND OPENINGS FORMED IN PHOTORESIST BY USE OF MULTIPLE DEVELOPMENT/RINSE CYCLES 审中-公开
标题翻译：通过使用多个开发/冲洗周期来减少在光电子装置中形成的开放后期的发展中缺陷的方法
公开(公告)号：WO0199161A2
公开(公告)日：2001-12-27
申请号：PCT/US0119815
申请日：2001-06-21
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： LU ZHIJIAN , THOMAS ALAN , GUTMANN ALOIS , CHEN KUANG JUNG , LAWSON MARGARET
IPC分类号： G03F7/30 , H01L21/00
CPC分类号： G03F7/3021
摘要： In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable remnants (denoted as Blob Defects) of various components of photoresist material remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of using a Puddle Development technique to develop the photoresist material, and subsequently exposing the semiconductor wafer to at least one Puddle Rinse cycle which uses water.
摘要翻译：在可用的深紫外（DUV）敏感光刻胶的曝光和显影中，已经观察到遵循现有技术的标准曝光和显影方法导致残留的光致抗蚀剂材料的各种组分的不希望的残留物（表示为Blob缺陷）的高密度在半导体基板（主体）上。曝光和显影光致抗蚀剂材料的方法导致这些Blob缺陷的发生率降低，包括使用水坑开发技术开发光致抗蚀剂材料，随后将半导体晶片暴露于使用水的至少一个水坑冲洗循环。

5. 发明专利

DE60142833D1 VERFAHREN ZUR VERRINGERUNG VON ENTWICKLUNGSDEFEKTEN IN UND UM ÖFFNUNGEN IN PHOTOLACK MITTELS MEHRFACHER ENTWICKLER/SPÜLZYKLEN 未知
公开(公告)号：DE60142833D1
公开(公告)日：2010-09-30
申请号：DE60142833
申请日：2001-06-21
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： LU ZHIJIAN , THOMAS ALAN , GUTMANN ALOIS , CHEN KUANG JUNG , LAWSON MARGARET
IPC分类号： G03F7/30

6. 发明专利

SG161185A1 CONTACT PATTERNING METHOD WITH TRANSITION ETCH FEEDBACK 未知
公开(公告)号：SG161185A1
公开(公告)日：2010-05-27
申请号：SG2009071069
申请日：2009-10-26
申请人： CHARTERED SEMICONDUCTOR MFG , SAMSUNG ELECTRONICS CO LTD , IBM , INFINEON TECHNOLOGIES CORP
发明人： BYUNG-GOO JEON , SUNG-CHUL PARK , EDLEMAN NIKKI , GUTMANN ALOIS , CHEN FANG
摘要： A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.

7. 发明专利

SG143124A1 SEMICONDUCTOR DEVICES HAVING PFET WITH SIGE GATE ELECTRODE AND EMBEDDED SIGE SOURCE/DRAIN REGIONS AND METHODS OF MAKING THE SAME 未知
公开(公告)号：SG143124A1
公开(公告)日：2008-06-27
申请号：SG2007162886
申请日：2007-10-01
申请人： CHARTERED SEMICONDUCTOR MFG , INFINEON TECHNOLOGIES CORP
发明人： FU CHONG YUNG , JINGYU LIAN , GUTMANN ALOIS , KNOEFLER ROMAN , JIANG YAN , STAPELMANN CHRIS , PING HAN JIN
摘要： Semiconductor Devices Having pFET with SiGe Gate Electrode and Embedded SiGe Source/Drain Regions and Methods of Making the Same In a method of making a semiconductor device, a first gate stack including a first gate electrode material is formed on a substrate at a pFET region. The PFET source/drain regions of the substrate and the first gate electrode material of the first gate stack at the pFET region are etched. The etching being at least partially selective so that the nFET region is shielded by a stress inducing mask layer formed thereon and so that a spacer structure of the pFET region at least partially retained. The etching forms PFET source/drain recesses and also removes at least part of the first gate electrode material at the pFET region providing a gate electrode recess. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is also achieved at the NFET from the stress inducing mask layer.

8. 发明专利

SG145648A1 METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES USING INSULATOR DEPOSITION AND INSULATOR GAP FILLING TECHNIQUES 未知
公开(公告)号：SG145648A1
公开(公告)日：2008-09-29
申请号：SG2008012403
申请日：2008-02-14
申请人： CHARTERED SEMICONDUCTOR MFG , SAMSUNG ELECTRONICS CO LTD , IBM , INFINEON TECHNOLOGIES AG
发明人： JUN-JUNG KIM , WIDODO JOHNNY , HUM KU JA , JAE-EON PARK , SUNFEI FANG , GUTMANN ALOIS , O-SUNG KWON , DAE-WON YANG
摘要： METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES USING INSULATOR DEPOSITION AND INSULATOR GAP FILLING TECHNIQUES Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

9. 发明专利

DE102009044377B4 Kontaktlochstrukturierungsverfahren mit Übergangsä ein derartiges zu implementieren 未知
公开(公告)号：DE102009044377B4
公开(公告)日：2012-05-31
申请号：DE102009044377
申请日：2009-10-30
申请人： CHARTERED SEMICONDUCTOR MFG , INFINEON TECHNOLOGIES AG , IBM , SAMSUNG ELECTRONICS CO LTD
发明人： CHEN FANG , EDLEMAN NIKKI , GUTMANN ALOIS , JEON BYUNG-GOO , PARK SUNG-CHUL
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/311 , H01L21/66 , H01L21/768
摘要： Verfahren zum Ausbilden eines Kontaktlochs in einer Halbleitervorrichtung, wobei das Verfahren aufweist: • Messen eines Prozentsatzes des Sauerstegeln des Prozentsatzes des Sauerstoffs in der Ätzkammer in der Weise, dass eine Polymerverengung oder polymerartige Verengung in der Nähe der Oberseite des Kontaktlochs verringert wird, ohne die Polymerverengung bzw. polymerartige Verengung zu beseitigen, wodurch ein vorübergehender Innendurchmesser in der Nähe der Oberseite des Kontaktlochs vergrößert wird.

10. 发明专利

DE102009044377A1 未知
公开(公告)号：DE102009044377A1
公开(公告)日：2010-05-20
申请号：DE102009044377
申请日：2009-10-30
申请人： CHARTERED SEMICONDUCTOR MFG , INFINEON TECHNOLOGIES AG , IBM , SAMSUNG ELECTRONICS CO LTD
发明人： CHEN FANG , EDLEMAN NIKKI , GUTMANN ALOIS , JEON BYUNG-GOO , PARK SUNG-CHUL
IPC分类号： H01L21/283

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