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1. 发明申请

WO2021001084A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2021001084A1
公开(公告)日：2021-01-07
申请号：PCT/EP2020/061972
申请日：2020-04-29
申请人： INFINEON TECHNOLOGIES AUSTRIA AG
发明人： KAHRIMANOVIC, Elvir , NOEBAUER, Gerhard , BLANK, Oliver , FERRARA, Alessandro
IPC分类号： H01L23/482 , H01L23/34 , H01L23/31 , H01L23/495 , H01L23/488 , H01L23/544
摘要： In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

2. 发明公开

EP3994725A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3994725A1
公开(公告)日：2022-05-11
申请号：EP20722579.8
申请日：2020-04-29
申请人： Infineon Technologies Austria AG
发明人： KAHRIMANOVIC, Elvir , NOEBAUER, Gerhard , BLANK, Oliver , FERRARA, Alessandro
IPC分类号： H01L23/482 , H01L23/34 , H01L23/31 , H01L23/495 , H01L23/488 , H01L23/544

3. 发明公开

EP3975225A1 SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP3975225A1
公开(公告)日：2022-03-30
申请号：EP20198168.5
申请日：2020-09-24
申请人： Infineon Technologies Austria AG
发明人： HOEGLAUER, Josef , NOEBAUER, Gerhard , KESSLER, Angela
IPC分类号： H01L21/60 , H01L23/538
摘要： In an embodiment, a semiconductor module is provided that comprises a laminate structure comprising an electrically insulating core layer (20) having a first side (21) and a second side (22) opposing the first side, a first redistribution layer (23) arranged on the first side and a second redistribution layer (24) arranged on the second side of the core layer. The semiconductor module further comprises a first transistor device (12) and a second vertical transistor device (13) coupled to form a half-bridge circuit. The first transistor device has a first side (25) at which a cell field (28) is arranged and a second side (27) opposing the first side, and the second transistor device has a first side (28) at which a cell field (29) is arranged and a second side (30) opposing the first side. The semiconductor module further comprises a control chip (14) having a first side (31) with contact pads (32). The first transistor device, the second transistor device and the control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip, the first side of one of the first and second transistor devices and the second side of the other one of the first and second transistor devices face towards the first redistribution layer on the first side of the core layer.

4. 发明公开

EP3982404A1 SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP3982404A1
公开(公告)日：2022-04-13
申请号：EP20200625.0
申请日：2020-10-07
申请人： Infineon Technologies Austria AG
发明人： FEHLER, Robert , KESSLER, Angela , NOEBAUER, Gerhard , PALM, Petteri , YUFEREV, Sergey
IPC分类号： H01L23/495
摘要： A semiconductor module is provided that comprises a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector comprises two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.

5. 发明公开

EP3907760A1 SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP3907760A1
公开(公告)日：2021-11-10
申请号：EP20173688.1
申请日：2020-05-08
申请人： Infineon Technologies Austria AG
发明人： NOEBAUER, Gerhard , YUFEREV, Sergey
IPC分类号： H01L25/07 , H01L23/498 , H01L23/66 , H01L23/00 , H01L23/64 , H01L23/538
摘要： In an embodiment a semiconductor module comprises a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a VIN package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further comprises a first capacitor pad coupled to ground potential and a second capacitor pad coupled to VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

6. 发明公开

EP4322222A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-实审
公开(公告)号：EP4322222A1
公开(公告)日：2024-02-14
申请号：EP22189507.1
申请日：2022-08-09
申请人： Infineon Technologies Austria AG
发明人： FERRARA, Alessandro , NOEBAUER, Gerhard
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78
摘要： The present application relates to a semiconductor device (1), comprising a field electrode (11) in a needle-shaped field electrode trench (12) extending from a frontside of a semiconductor body (10) into the semiconductor body (10), a lower metallization layer (20) on the frontside of the semiconductor body (10), electrically connected to the field electrode (11), an insulating layer (30) on the lower metallization layer (20), an upper metallization layer (40) on the insulating layer (30), a first interconnect (105.1) electrically connecting the lower metallization layer (20) to the upper metallization layer (40), wherein the first interconnect (105.1) is laterally offset to the field electrode trench (12), the lower metallization layer (20) being not connected to the upper metallization layer (40) in a region (15) vertically above the field electrode trench (12).

7. 发明公开

EP3761357A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3761357A1
公开(公告)日：2021-01-06
申请号：EP19184547.8
申请日：2019-07-04
申请人： Infineon Technologies Austria AG
发明人： BLANK, Oliver , NOEBAUER, Gerhard
IPC分类号： H01L23/482 , H01L23/31
摘要： In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure comprises a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode.

8. 发明公开

EP3703123A1 SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR PACKAGE 有权
公开(公告)号：EP3703123A1
公开(公告)日：2020-09-02
申请号：EP19159762.4
申请日：2019-02-27
申请人： Infineon Technologies Austria AG
发明人： MIRCHANDANI, Ashita , NOEBAUER, Gerhard
IPC分类号： H01L23/495
摘要： In an embodiment, a semiconductor package is provided that comprises at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device comprises a first transistor device having a source electrode, a gate electrode and a drain electrode, a front surface and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization comprises a first power contact pad coupled to the source electrode, the first power contact pad being mounted on the die pad. The rear metallization comprises a second power contact pad electrically coupled to the drain electrode and an auxiliary lateral redistribution structure that is electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.

9. 发明公开

EP4432359A1 SEMICONDUCTOR DIE WITH A VERTICAL DEVICE 审中-实审
公开(公告)号：EP4432359A1
公开(公告)日：2024-09-18
申请号：EP23161807.5
申请日：2023-03-14
申请人： Infineon Technologies Austria AG
发明人： NOEBAUER, Gerhard , FERRARA, Alessandro , YUFEREV, Sergey , GASSER, Florian
IPC分类号： H01L27/06 , H01L29/417 , H01L29/78
CPC分类号： H01L27/0629 , H01L29/7804 , H01L29/41766 , H01L29/7813 , H01L29/7808 , H01L29/7803
摘要： The disclosure relates to a semiconductor die (1) with a semiconductor body (2), the semiconductor die (1) comprising a vertical transistor device (10) formed in a first area (11) of the semiconductor body (2), the vertical transistor device (10) comprising a source region (15) at a first side (2.1) of the semiconductor body (2), and a drain region (16) at a second side (2.2) of the semiconductor body (2); a first electrical isolation (40) between the first area (11) and a second area (12) of the semiconductor body (2); and a diode (50) in the second area (12) of the semiconductor body (2); wherein a cathode contact (62) of the diode (50) is electrically connected to the source region (15) of the vertical transistor device (10).

10. 发明公开

EP4310907A1 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE FOR UPRIGHT MOUNTING 审中-实审
公开(公告)号：EP4310907A1
公开(公告)日：2024-01-24
申请号：EP22186561.1
申请日：2022-07-22
申请人： Infineon Technologies Austria AG
发明人： HOEGLAUER, Josef , NOEBAUER, Gerhard , YUFEREV, Sergey , ZHUANG, Hao
IPC分类号： H01L23/495
摘要： In an embodiment, a semiconductor package comprises a low voltage contact pad, a high voltage contact pad, an output contact pad, a half-bridge circuit and a first, a second and a third lead. The half bridge circuit comprises a first transistor device and a second transistor device coupled in series at an output node. The first transistor device has a first major surface and the second transistor device has a first major surface and the first major surface of the first transistor device and of the second transistor device extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad and the output contact pad. The first and second transistor devices are arranged in a device portion of the semiconductor package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.

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