专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

DE102004017411B4 未知
公开(公告)号：DE102004017411B4
公开(公告)日：2010-01-07
申请号：DE102004017411
申请日：2004-04-08
申请人： INFINEON TECHNOLOGIES AG , IBM , UNITED MICROELECTRONICS CO
发明人： COWLEY ANDY , FANG SUNFEI , WANG YUN-YU , CLEVENGER LARRY , SIMON ANDREW H , GRECO STEPHEN , CHANDA KAUSHIK , SPOONER TERRY , YANG CHIH-CHAO
IPC分类号： H01L21/285 , H01L21/768

2. 发明专利

DE102004028026B4 未知
公开(公告)号：DE102004028026B4
公开(公告)日：2006-08-10
申请号：DE102004028026
申请日：2004-06-09
申请人： INFINEON TECHNOLOGIES AG , IBM
发明人： KUMAR KAUSHIK , CLEVENGER LARRY , DALTON TIMOTHY J , LA TULIPE DOUGLAS C , COWLEY ANDY , KALTALIOGLU ERDEM , SCHACHT JOCHEN , HOINKIS MARK , SIMON ANDREW H , KALDOR STEFFEN , YANG CHIH-CHAO
IPC分类号： H01L21/3213 , H01L21/033 , H01L21/311 , H01L21/768

3. 发明专利

DE102004028026A1 未知
公开(公告)号：DE102004028026A1
公开(公告)日：2005-02-03
申请号：DE102004028026
申请日：2004-06-09
申请人： INFINEON TECHNOLOGIES AG , IBM
发明人： KUMAR KAUSHIK , CLEVENGER LARRY , DALTON TIMOTHY J , LA TULIPE DOUGLAS C , COWLEY ANDY , KALTALIOGLU ERDEM , SCHACHT JOCHEN , HOINKIS MARK , SIMON ANDREW H , KALDOR STEFFEN , YANG CHIH-CHAO
IPC分类号： H01L21/033 , H01L21/311 , H01L21/768 , H01L21/3213

4. 发明专利

DE102004017411A1 未知
公开(公告)号：DE102004017411A1
公开(公告)日：2005-03-10
申请号：DE102004017411
申请日：2004-04-08
申请人： INFINEON TECHNOLOGIES AG , IBM , UNITED MICROELECTRONICS CO
发明人： COWLEY ANDY , FANG SUNFEI , WANG YUN-YU , CLEVENGER LARRY , SIMON ANDREW H , GRECO STEPHEN , CHANDA KAUSHIK , SPOONER TERRY , YANG CHIH-CHAO
IPC分类号： H01L21/768 , H01L21/285

5. 发明申请

WO2005038880A3 VIA DENSITY RULES 审中-公开
标题翻译：维多利亚规则
公开(公告)号：WO2005038880A3
公开(公告)日：2005-08-25
申请号：PCT/EP2004052411
申请日：2004-10-01
申请人： INFINEON TECHNOLOGIES AG , COWLEY ANDY , FAYAZ MOHAMMED FAZIL , HIERLEMANN MATTHIAS , HOINKIS MARK , KALTALIOGLU ERDEM
发明人： COWLEY ANDY , FAYAZ MOHAMMED FAZIL , HIERLEMANN MATTHIAS , HOINKIS MARK , KALTALIOGLU ERDEM
IPC分类号： G06F17/50 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Thermo- mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.
摘要翻译：通孔上的热机械应力降低，从而减少相关故障。这可以通过保持通孔至金属面积比至少等于预定值以下，通孔上的附加应力不会显着增加的程度来实现。

6. 发明专利

DE102004028057B4 Verfahren zur Ausbildung einer zusammengesetzten intermetallischen dielektrischen Struktur 未知
公开(公告)号：DE102004028057B4
公开(公告)日：2015-12-17
申请号：DE102004028057
申请日：2004-06-09
申请人： INFINEON TECHNOLOGIES AG
发明人： COWLEY ANDY , NAUJOK MARKUS , KIM SUN-OO
IPC分类号： H01L21/768 , H01L21/3105 , H01L21/314
摘要： Verfahren zur Ausbildung einer zusammengesetzten intermetallischen dielektrischen Struktur, mit: Bereitstellen einer anfänglichen intermetallischen dielektrischen Struktur mit einer ersten dielektrischen Schicht (21) und zwei Leiterbahnen (26), wobei die zwei Leiterbahnen (26) sich in der ersten dielektrischen Schicht (21) befinden; Entfernen eines Abschnitts der ersten dielektrischen Schicht zwischen den Leiterbahnen (26) zum Ausbilden einer Vertiefung (40), wobei die anfängliche intermetallische dielektrische Struktur ferner eine Hartmaskenschicht (24) oben auf der ersten dielektrischen Schicht (21) umfasst, und wobei das Entfernen des Abschnitts der ersten dielektrischen Schicht (21) ein Entfernen eines Abschnitts der Hartmaskenschicht (24) zum Ausbilden der Vertiefung umfasst; Füllen der Vertiefung (40) mit einem zweiten dielektrischen Material (52), wobei das zweite dielektrische Material (52) ein Dielektrikum mit niedrigem k ist, das eine geringere Dielektrizitätskonstante als die der ersten dielektrischen Schicht (21) aufweist; Durchführen eines Planarisierungsprozesses nach dem Füllen, zum Erzeugen einer planaren oberen Fläche (54); Zurücksetzen des zweiten dielektrischen Materials (52) und der Hartmaske (24) relativ zu den Leiterbahnen (26), so dass sie unterhalb der oberen Fläche (54) liegen; und Bedecken mit einer Abdeckschicht (58).

7. 发明专利

DE102004005697B4 未知
公开(公告)号：DE102004005697B4
公开(公告)日：2007-03-29
申请号：DE102004005697
申请日：2004-02-05
申请人： INFINEON TECHNOLOGIES AG
发明人： COWLEY ANDY , STETTER MICHAEL , KALTALIOGLU ERDEM
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

8. 发明专利

DE102004010352B4 未知
公开(公告)号：DE102004010352B4
公开(公告)日：2006-10-19
申请号：DE102004010352
申请日：2004-03-03
申请人： INFINEON TECHNOLOGIES AG
发明人： COWLEY ANDY , HOINKIS MARK , KALTALIOGLU ERDEM , STETTER MICHAEL
IPC分类号： H01L21/768
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

9. 发明专利

DE102004005697A1 未知
公开(公告)号：DE102004005697A1
公开(公告)日：2004-08-26
申请号：DE102004005697
申请日：2004-02-05
申请人： INFINEON TECHNOLOGIES AG
发明人： COWLEY ANDY , STETTER MICHAEL , KALTALIOGLU ERDEM
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

10. 发明专利

DE102004010352A1 未知
公开(公告)号：DE102004010352A1
公开(公告)日：2004-09-23
申请号：DE102004010352
申请日：2004-03-03
申请人： INFINEON TECHNOLOGIES AG
发明人： COWLEY ANDY , HOINKIS MARK , KALTALIOGLU ERDEM , STETTER MICHAEL
IPC分类号： H01L21/768
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式