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1. 发明申请

WO02059898A2 MRAM ARRANGEMENT 审中-公开
标题翻译： MRAM安排
公开(公告)号：WO02059898A2
公开(公告)日：2002-08-01
申请号：PCT/DE0200207
申请日：2002-01-23
申请人： INFINEON TECHNOLOGIES AG , FREITAG MARTIN , ROEHR THOMAS
发明人： FREITAG MARTIN , ROEHR THOMAS
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L27/22
CPC分类号： H01L27/228 , G11C11/16
摘要： The invention relates to an MRAM arrangement in which the selection transistors (5) and the MTJ layer sequences (4) lie parallel to each other in a cell. A considerable space saving can thus be achieved.
摘要翻译：本发明涉及，其中，选择晶体管（5）和所述MTJ层序列（4）位于细胞平行于彼此，一个MRAM阵列。这实现了显著面积节省。

2. 发明申请

WO2004051666A3 REDUCING EFFECTS OF NOISE COUPLING IN INTEGRATED CIRCUITS WITH MEMORY ARRAYS 审中-公开
标题翻译：噪声耦合在集成电路与存储器阵列中的降低效应
公开(公告)号：WO2004051666A3
公开(公告)日：2005-02-24
申请号：PCT/EP0312715
申请日：2003-11-13
申请人： INFINEON TECHNOLOGIES AG , TOSHIBA KK , JACOB MICHAEL , REHM NORBERT , ROEHR THOMAS , TAKASHIMA DAISABURO
发明人： JACOB MICHAEL , REHM NORBERT , ROEHR THOMAS , TAKASHIMA DAISABURO
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
摘要翻译：公开了一种减少存储器阵列中的噪声耦合的方法。存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。存储器单元被布置成具有耦合到读出放大器的第一和第二位线的列。在存储器访问期间，至少相邻的位线对不被激活。选定的位线对或对配有一条平行线脉冲。

3. 发明申请

WO0239455A8 MRAM ARRANGEMENT WITH SELECTION TRANSISTORS OF LARGE CHANNEL WIDTH 审中-公开
公开(公告)号：WO0239455A8
公开(公告)日：2002-10-17
申请号：PCT/DE0104232
申请日：2001-11-12
申请人： INFINEON TECHNOLOGIES AG , BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
发明人： BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.

4. 发明申请

WO2004047116A8 2T2C SIGNAL MARGIN TEST MODE USING DIFFERENT PRE-CHARGE LEVELS FOR BL AND /BL 审中-公开
标题翻译： 2T2C信号测试模式使用不同的预充电水平进行BL和/ BL
公开(公告)号：WO2004047116A8
公开(公告)日：2004-08-26
申请号：PCT/SG0300263
申请日：2003-11-11
申请人： INFINEON TECHNOLOGIES AG , JACOB MICHAEL , ROEHR THOMAS , WOHLFAHRT JOERG , JOACHIM HANS-OLIVER
发明人： JACOB MICHAEL , ROEHR THOMAS , WOHLFAHRT JOERG , JOACHIM HANS-OLIVER
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effect into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A potential is connected to the first bit line through a third transistor and changes a pre-charge signal level on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进信号余量的最坏情况产品测试序列，以确保在整个组件使用寿命期内产生全部产品功能，从而考虑到所有的老化效应。半导体存储器测试模式配置包括用于存储数字数据的第一电容器。电容器通过第一选择晶体管将单元板线连接到第一位线。第一个选择晶体管通过与字线的连接来激活。第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。第二选择晶体管也通过与字线的连接来激活。读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。电位通过第三晶体管连接到第一位线，并且当第三晶体管导通时改变第一位线上的预充电信号电平以减小差分读取信号。

5. 发明申请

WO0239455A2 MRAM ARRANGEMENT WITH SELECTION TRANSISTORS OF LARGE CHANNEL WIDTH 审中-公开
标题翻译：具有大通道宽度选择晶体管的MRAM安排
公开(公告)号：WO0239455A2
公开(公告)日：2002-05-16
申请号：PCT/DE0104232
申请日：2001-11-12
申请人： INFINEON TECHNOLOGIES AG , BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
发明人： BOEHM THOMAS , HOENIGSCHMID HEINZ , ROEHR THOMAS
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.
摘要翻译：本发明涉及一种MRAM装置，其中选择晶体管（T）被分配给多个MTJ存储单元（1）并且具有增加的沟道宽度。

6. 发明申请

WO2004047117A8 2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE AND DISCHARGE OF BL AND /BL 审中-公开
标题翻译： 2T2C信号测试模式使用定义的充电和放电BL和/ BL
公开(公告)号：WO2004047117A8
公开(公告)日：2004-08-19
申请号：PCT/SG0300264
申请日：2003-11-11
申请人： INFINEON TECHNOLOGIES AG , JOACHIM HANS-OLIVER , ROEHR THOMAS , WOHLFAHRT JOERG
发明人： JOACHIM HANS-OLIVER , ROEHR THOMAS , WOHLFAHRT JOERG
IPC分类号： G11C29/50 , G11C29/00 , G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进用于信号余量的最坏情况产品测试序列，以确保整个组件寿命期间的全部产品功能，从而考虑所有老化效应。半导体存储器测试模式配置包括用于存储数字数据的第一电容器。第一电容器通过第一选择晶体管将单元板线连接到第一位线。第一个选择晶体管通过与字线的连接来激活。用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线。第二选择晶体管也通过与字线的连接来激活。感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。

7. 发明申请

WO0001010A3 METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：用于生产半导体器件
公开(公告)号：WO0001010A3
公开(公告)日：2002-10-03
申请号：PCT/DE9901770
申请日：1999-06-16
申请人： INFINEON TECHNOLOGIES AG , ROEHR THOMAS , MAZURE-ESPEJO CARLOS , DEHM CHRISTINE
发明人： ROEHR THOMAS , MAZURE-ESPEJO CARLOS , DEHM CHRISTINE
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/3213 , H01L21/8242 , H01L27/108 , H01L21/033
CPC分类号： H01L28/60 , H01L21/32139 , H01L2924/0002 , Y10S438/95 , H01L2924/00
摘要： Disclosed is a method for producing semiconductor elements comprising a metal layer (10) arranged on a semiconductor substrate . The inventive method consists of the following steps: a silicon layer (30) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (30); the silicon layer is selectively etched (30) using said etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (30) as a hard mask.
摘要翻译：提出一种包括用于制造半导体器件的方法的步骤具有布置在半导体衬底金属层上（10）：所述金属层（10）上沉积硅层（30）; 施加的蚀刻掩模（25），用于图案化所述硅层（30）; 选择性地蚀刻使用蚀刻掩模（25）的硅层（30）; 以及使用该选择性地蚀刻硅层（30）作为硬掩模在蚀刻工艺图案化所述金属层（10）。

8. 发明专利

JP2004199238A Semiconductor device and its starting method 有权
公开(公告)号：JP2004199238A
公开(公告)日：2004-07-15
申请号：JP2002364902
申请日：2002-12-17
申请人： Infineon Technologies Ag , Toshiba Corp , インフィネオンテクノロジースアクチエンゲゼルシャフト , 株式会社東芝
发明人： OIKAWA KOHEI , SHIRATAKE SHINICHIRO , TAKASHIMA DAIZABURO , TAKEUCHI YOSHIAKI , ROEHR THOMAS
IPC分类号： G11C11/41 , G06F1/24 , G06F12/16 , G11C7/20 , G11C16/02 , H03K17/22
CPC分类号： G11C7/20
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve the reliability of a reading-out operation immediately after turning on the power, and its starting method.
SOLUTION: The semiconductor device 10 comprises an internal power supply 30 which outputs an initialization completion signal POR when initialized, at least one semiconductor circuit block 20 which operates based on a voltage generated by the internal power supply 30, a delay circuit 40 which delays the initialization completion signal POR, and detection circuits 50 and 60 which command the operation starting to the semiconductor circuit block 20 in response to the initialization completion signal DPOR delayed in the delay circuit 40 and a first input signal CE input from the external.
COPYRIGHT: (C)2004,JPO&NCIPI

9. 发明专利

JP2004013987A Semiconductor storage device 审中-公开
公开(公告)号：JP2004013987A
公开(公告)日：2004-01-15
申请号：JP2002165286
申请日：2002-06-06
申请人： Infineon Technologies Ag , Toshiba Corp , インフィネオンテクノロジースアクチエンゲゼルシャフト , 株式会社東芝
发明人： MIYAGAWA TADASHI , TAKASHIMA DAIZABURO , ROEHR THOMAS
IPC分类号： G01R31/28 , G01R31/3185 , G11C7/22 , G11C29/14 , G11C29/50 , G11C29/00
CPC分类号： G11C29/50012 , G11C7/22 , G11C29/50
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory chip for allowing the internal function to be easily analyzed as the most important feature. SOLUTION: For example, when a test mode is set, an output test signal RWTEST is outputted from a test control circuit 32 to a switch circuit section 31. Then, a plurality of timing control signals (Si) inside of a chip are converted to data Di in the switch circuit section 31, and sent to a data input/output buffer circuit section 23. Thereby, the plurality of timing control signals (Si) are outputted simultaneously from a plurality of data input/output terminals I/Oi used for input/output of cell data (Di). COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2001307478A INTEGRATED MEMORY, AND METHOD FOR GENERATING REFERENCE VOLTAGE ON REFERENCE BIT LINE OF INTEGRATED MEMORY 失效
公开(公告)号：JP2001307478A
公开(公告)日：2001-11-02
申请号：JP2001083633
申请日：2001-03-22
申请人： INFINEON TECHNOLOGIES AG
发明人： BOEHM THOMAS , MANYOKI ZOLTAN , ESTERL ROBERT , ROEHR THOMAS
IPC分类号： G11C11/22
摘要： PROBLEM TO BE SOLVED: To improve accuracy of bit line reference voltage to read and write data in a memory capacitor MC in a memory in which a differential sense amplifier SA is connected to a pair of bit lines, for example, a ferroelectric memory to read and write data in a memory capacitor MC. SOLUTION: A main reference bit line/BL0 is connected to reference voltage VREF through a charging switch element TL. The other reference bit line/BLi is connected to the main bit line/BL0 through a balance adjusting switch element TA for electric charges balance adjustment between parasitic capacitance of each reference bit line. At the time, reference voltage VGEN is separated from the main reference bit line/BL0, other reference bit lines /BL1, /BL2, /BL3 are connected to the main reference bit line in parallel. Thereby, balance adjustment of electric charges accumulated in parasitic capacitance CPi of each reference bit line connected in parallel is performed, reference voltage VREF is distributed as equal plural bit line reference voltage V/BLi.

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