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1. 发明申请

WO0159845A2 BIPOLAR TRANSISTOR 审中-公开
标题翻译：双极型晶体管
公开(公告)号：WO0159845A2
公开(公告)日：2001-08-16
申请号：PCT/EP0101324
申请日：2001-02-07
申请人： INFINEON TECHNOLOGIES AG , FRANOSCH MARTIN , SCHAEFER HERBERT , MEISTER THOMAS , STENGL REINHARD
发明人： FRANOSCH MARTIN , SCHAEFER HERBERT , MEISTER THOMAS , STENGL REINHARD
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/7322
摘要： The invention relates to a bipolar transistor (20) and to a method for producing the same. In order to obtain an as low a transition resistance as possible between the feed line (51) and the base (42), an intermediate layer (70) is provided between the first (30) and the second (40) layer, said intermediate layer (70) being selectively etchable to the second layer (40). At least in the zone of the undercut (43) between the feed line (51) and the base (42) a base connection zone (45) is provided that can be adjusted independent of other production conditions. The inventive transistor is further characterized in that the intermediate layer (70) is removed in the contact zone (46) with the base (42).
摘要翻译：公开了一种双极型晶体管（20），以及用于其生产的方法。所述双极晶体管（20）具有在其中设置的收集器（31）的第一，在基板（10）位于层（30），位于一个所述第一层（30）上的第二层（40）（碱切口 41）具有基部（42），至少一个另外的第三层（50）（第二层40上）设置并且其具有用于所述基部（42），其中，所述进料管线的进料管线（51）（51 ）（在过渡区域52），以直接接触的所述基部（42），并且其中所述第三层（50）具有一个具有发射极的发射极的切口（53），和至少一个底切（43），其在所述第二层（40）下面的所述第一（30）和第三之间的基底切口（41）（50）层设置，其特征在于，所述基部（42）至少部分地在所述底切（43）。为了获得所述供应管线（51）和底座（42）之间的最低可能的过渡电阻，根据它提供的是，第一（30）之间的本发明和第二（40）层，中间层（70）设置，所述中间层（70）选择性地形成以蚀刻第二层（40），至少在该底切之间（43）供应线（51）和基座（42）的基极端子区域（45）被提供，其可被调节的独立于其他制造条件的区域中，并且该中间层（70）位于所述接触区（46）与所述基部（42）。

2. 发明申请

WO03036723A2 SEMICONDUCTOR STRUCTURE PROVIDED WITH A COMPONENT CAPACITIVELY UNCOUPLED FROM THE SUBSTRATE 审中-公开
标题翻译： WITH A衬底能力去耦分量的半导体结构
公开(公告)号：WO03036723A2
公开(公告)日：2003-05-01
申请号：PCT/EP0209705
申请日：2002-08-30
申请人： INFINEON TECHNOLOGIES AG , BOECK JOSEF , MEISTER THOMAS , SCHAEFER HERBERT , STENGL REINHARD
发明人： BOECK JOSEF , MEISTER THOMAS , SCHAEFER HERBERT , STENGL REINHARD
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L27/06
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： The invention concerns a semiconductor structure comprising a substrate (10), an insulating layer (14) arranged on one surface of the substrate (10), a layer (18) for components arranged on one surface (16) of the insulating layer (14) opposite the substrate (10), a semiconductor component (30a, 30b) arranged in the layer (18) for components and zone designed for capacitively uncoupling said semiconductor component (30a, 30b) relative to the substrate (10), said zone being formed by a space charge zone (96) formed in a region of the substrate (10) adjacent to the insulating layer (14).
摘要翻译：一种半导体结构，包括衬底（10），其被布置在所述基板（10），该表面面向远离所述基板的一个（10）的器件层（18）的一个表面（12）上的绝缘层（14）（16）在绝缘层（14）设置，半导体装置（30A，30B），其是所述器件层（18）设置，以及用于半导体装置的电容性耦合的区域（30A，30B）在基板（10）的，通过在形成于基板（10）空间电荷区中的绝缘层（14）区域中的相邻的一个（96）形成。

3. 发明申请

WO0002249A3 INTEGRATED CIRCUIT WITH P-N JUNCTIONS WITH REDUCED DEFECTS 审中-公开
标题翻译： INTEGRATED CIRCUIT WITH P-N转变WITH减少的缺陷
公开(公告)号：WO0002249A3
公开(公告)日：2000-03-16
申请号：PCT/DE9901934
申请日：1999-07-01
申请人： SIEMENS AG , STENGL REINHARD , FRANOSCH MARTIN , SCHAEFER HERBERT , LEHMANN VOLKER , REISINGER HANS , WENDT HERMANN
发明人： STENGL REINHARD , FRANOSCH MARTIN , SCHAEFER HERBERT , LEHMANN VOLKER , REISINGER HANS , WENDT HERMANN
IPC分类号： H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/04
CPC分类号： H01L27/10844 , H01L27/10805 , H01L29/045
摘要： The inventive integrated circuit comprises at least one first component with a structure to which defects may be adjacent and a second component with at least one p-n junction (Ü'), said components being situated next to each other in a substrate (1) whose defects extend in a defect plane (d) at least in sections. The crystal orientation of the substrate (1) in relation to the first component and the second component is chosen with the aim of keeping the defects on the surfaces without them intersecting the p-n junction (Ü'), in order to prevent undesirable leakage currents through the p-n junction (Ü'). The integrated circuit is especially a DRAM cell arrangement with extended retention time. The inventive integrated circuit is produced by mounting photo-resist masks of a known layout on the starting wafer, the masks being rotated in relation to a known starting wafer. Alternatively, photo-resist masks of a known layout can be mounted on a starting wafer in a conventional manner, the output wafer having a marking showing the course of the defect plane (d).
摘要翻译：所述集成电路装置包括至少在一个基片具有可以在邻近缺陷彼此相邻的结构，并且具有至少一个pn结（B“）的第二组分的第一组分（1）被布置，其至少缺陷部分中缺陷电平（d）延伸。被选择的衬底（1）相对于所述第一组分和所述第二组分的晶体取向，使得缺陷被记录在表面上而不被切断p-n结。以这种方式，能够避免通过p-n结（B“）不希望的泄漏。集成电路装置是特别具有增加的保留时间的DRAM单元的布置。为了制备集成电路装置光刻胶掩模可以被安装在一个已知的晶片布局相对于扭转的已知的起始晶片的输出。可替代地，光致抗蚀剂掩模的已知布局可以在输出晶片上以常规方式应用，但起始晶片具有示出的缺陷电平（d）的过程中的标签。

4. 发明申请

WO9965063A3 DRAM STORAGE CAPACITOR 审中-公开
标题翻译：存储器，用于电容器DRAM
公开(公告)号：WO9965063A3
公开(公告)日：2000-03-16
申请号：PCT/DE9901454
申请日：1999-05-12
申请人： SIEMENS AG , REISINGER HANS , LEHMANN VOLKER , STENGL REINHARD , WENDT HERMANN , LANGE GERRIT , BACHHOFER HARALD , FRANOSCH MARTIN , SCHAEFER HERBERT
发明人： REISINGER HANS , LEHMANN VOLKER , STENGL REINHARD , WENDT HERMANN , LANGE GERRIT , BACHHOFER HARALD , FRANOSCH MARTIN , SCHAEFER HERBERT
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10805
摘要： (57) Abstract The invention relates to a DRAM storage capacitor, comprising a dielectric made of silicon nitride and at least two electrodes placed opposite to each other above the dielectric. A material with higher tunnel barrier ( phi beta ) between the Fermi level (F) of the material and the conduction band (L) of the dielectric is used for the electrodes. For said purpose, the appropriate materials are metals such a platinum, tungsten and iridium or silicide. (57) Zusammenfassung Die Erfindung betrifft einen Speicherkondensator für einen DRAM, mit einem aus Siliziumnitrid bestehenden Dielektrikum und mit wenigstens zwei, über das Dielektrikum einander gegenüberliegenden Elektroden. Für die Elektroden wird ein Material mit hoher Tunnelbarriere ( phi beta ) zwischen Fermi-Niveau (F) des Materials und Leitungsband (L) des Dielektrikums verwendet. Geeignete Materialien sind hierfür Metalle wie Platin, Wolfram und Iridium oder Silizide.
摘要翻译：本发明涉及一种存储电容器用于DRAM，包括由氮化硅的电介质构成的组，和具有至少两个电极在所述电介质彼此相对。对于使用电介质的材料具有高的隧道势垒（PHI测试版）的材料和导带（L）的费米能级（F）之间的电极。用于此目的的合适的材料是金属，例如铂，钨，和铱，或硅化物。

5. 发明专利

DE50115869D1 Verfahren zur Herstellung eines Bipolartransistors 未知
公开(公告)号：DE50115869D1
公开(公告)日：2011-06-16
申请号：DE50115869
申请日：2001-02-07
申请人： INFINEON TECHNOLOGIES AG
发明人： FRANOSCH MARTIN , SCHAEFER HERBERT , MEISTER THOMAS , STENGL REINHARD
IPC分类号： H01L29/732 , H01L21/331

6. 发明专利

DE19947117B4 未知
公开(公告)号：DE19947117B4
公开(公告)日：2007-03-08
申请号：DE19947117
申请日：1999-09-30
申请人： INFINEON TECHNOLOGIES AG
发明人： STENGL REINHARD , REISINGER HANS , HANEDER THOMAS , BACHHOFER HARALD
IPC分类号： H01L21/8247 , H01L29/78 , G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/51 , H01L29/788 , H01L29/792
摘要： A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

7. 发明专利

DE59913465D1 未知
公开(公告)号：DE59913465D1
公开(公告)日：2006-06-29
申请号：DE59913465
申请日：1999-07-05
申请人： INFINEON TECHNOLOGIES AG
发明人： HANEDER PETER , REISINGER HANS , STENGL REINHARD , BACHHOFER HARALD , WENDT HERMANN , HOENLEIN WOLFGANG
IPC分类号： H01L21/8247 , H01L29/786 , G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792
摘要： A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

8. 发明专利

DE10220578A1 Bipolar transistor used as a self-adjusting bipolar transistor comprises an emitter region electrically contacted via an emitter electrode, a base region electrically contacted 未知
公开(公告)号：DE10220578A1
公开(公告)日：2003-11-27
申请号：DE10220578
申请日：2002-05-08
申请人： INFINEON TECHNOLOGIES AG
发明人： BOECK JOSEF , FRANOSCH MARTIN , SCHAEFER HERBERT , STENGL REINHARD , MEISTER THOMAS
IPC分类号： H01L29/45 , H01L29/737 , H01L29/732 , H01L29/73
摘要： Bipolar transistor comprises an emitter region (3) electrically contacted via an emitter electrode (1), a base region (4) electrically contacted via a base electrode (2), and a collector region (5) electrically contacted via a collector electrode. At least one of the electrodes contains silicon-germanium.

9. 发明专利

DE10104776A1 未知
公开(公告)号：DE10104776A1
公开(公告)日：2002-08-22
申请号：DE10104776
申请日：2001-02-02
申请人： INFINEON TECHNOLOGIES AG
发明人： STENGL REINHARD , MEISTER THOMAS F , SCHAEFER HERBERT , FRANOSCH MARTIN
IPC分类号： H01L21/331 , H01L29/737 , H01L29/73 , H01L29/732
摘要： The invention relates to a method for producing a bipolar transistor having low base terminal resistance, a low defect density, and improved scalability, scalability referring to both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be maintained at a low level in the base area, as no implantations are required in order to reduce the base terminal resistance. Furthermore, the difficulties related to point defects are largely avoided.

10. 发明专利

DE59704768D1 未知
公开(公告)号：DE59704768D1
公开(公告)日：2001-11-08
申请号：DE59704768
申请日：1997-06-24
申请人： INFINEON TECHNOLOGIES AG
发明人： SCHAEFER HERBERT , FRANOSCH MARTIN , STENGL REINHARD , LEHMANN VOLKER , REISINGER HANS , WENDT HERMANN
IPC分类号： C23C16/04 , H01L21/033 , H01L21/20 , H01L21/205 , H01L21/266 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/3205 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L27/11517 , H01L29/788 , H01L29/792
摘要： The mfg. method provides a fine structure at the surface of a substrate (1,2,3) using a cathodic vapour deposition process, effected with a process gas containing SiH4 and GeH4 in a carrier gas, for providing raised areas (4) determining the size of the fine structures. The raised areas act as a mask for an etching or implantation process and have a mean dia. and mean spacing of the order of between 1 and 100nm.

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