专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO03007304A2 MAGNETIC MEMORY UNIT AND MAGNETIC MEMORY ARRAY 审中-公开
标题翻译：磁存储单元和磁存储阵列
公开(公告)号：WO03007304A2
公开(公告)日：2003-01-23
申请号：PCT/DE0202458
申请日：2002-07-04
申请人： INFINEON TECHNOLGIES AG , HOENLEIN WOLFGANG , KREUPL FRANZ
发明人： HOENLEIN WOLFGANG , KREUPL FRANZ
IPC分类号： B82B1/00 , G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L29/06 , H01L43/08
CPC分类号： B82Y10/00 , G11C11/14 , G11C11/16 , G11C13/025 , H01L27/222 , H01L43/08
摘要： The invention relates to a magnetic memory unit and a magnetic memory array. Said magnetic memory unit has a first magnetizable electrode, a second magnetizable electrode and at least one nanotube, which is positioned in a longitudinal direction between the electrodes and is coupled at its first longitudinal end to the first electrode and at its second longitudinal end to the second electrode. The magnetic memory array has numerous magnetic memory units.
摘要翻译：磁存储单元和磁存储阵列磁存储装置包括其上在纵向方向上被设置在电极之间，并且与所述第一电极耦接，其第一纵向端部，并与它的第二纵向端至所述第二电极的第一可磁化电极，第二磁化电极，和至少一个纳米管。磁存储器阵列具有多个磁存储单元。

2. 发明申请

WO03050868A3 METHOD FOR PRODUCING A LAYERED ASSEMBLY AND A LAYERED ASSEMBLY 审中-公开
标题翻译：一种用于生产层排列和层排列
公开(公告)号：WO03050868A3
公开(公告)日：2003-09-04
申请号：PCT/DE0203998
申请日：2002-10-23
申请人： INFINEON TECHNOLOGIES AG , KREUPL FRANZ , HOENLEIN WOLFGANG , STEINHOEGL WERNER
发明人： KREUPL FRANZ , HOENLEIN WOLFGANG , STEINHOEGL WERNER
IPC分类号： H01L21/768 , H01L51/30 , C01B31/02 , H01L23/522
CPC分类号： H01L21/7682 , B82Y10/00 , H01L51/0048 , H01L2221/1047 , Y10S977/742
摘要： The invention relates to a method for producing a layered assembly and to a layered assembly (200). According to said method, two substantially parallel electrically conductive strip conductors (202, 203) are configured on a substrate and at least one auxiliary structure (205a, 205b, 205c) is configured on said substrate (201) between the two strip conductors (202, 203), running in a first direction (206), said first direction (206) forming an acute angle of at least 45 DEG or a right angle with a connecting axis of the strip conductors that runs at right angles to both strip conductors (202, 203). The invention is characterised in that the auxiliary structure or structures (205a, 205b, 205c) is or are produced from one material and said structure or structures can be selectively removed from the dielectric layer (204). In addition, a dielectric layer (204) is configured between the two strip conductors in such a way that the auxiliary structure or structures (205a, 205b, 205c) is or are at least partially covered by the dielectric layer (204).
摘要翻译：本发明涉及一种用于制造层结构的方法，和层布置。在用于制造层结构（200），两个基本上相互平行的导电迹线（202,203）的方法形成在衬底上的衬底，至少一个辅助结构（205A，205B，205C）上（201）且沿第一方向延伸的两个导体（202，203）之间（206）形成，该第一方向（206）与垂直于延伸的互连的连接轴线的锐角或直角两个互连（202，203）至少包括45°的角度，其中，所述至少一个辅助结构（205A，205B，205C）由介电层（204）的至少一个辅助结构是可选择性去除的材料制成。此外，在两个导体轨道之间形成的介电层（204），使得从电介质层（204）的所述至少一个辅助结构（205A，205B，205C）至少部分地被覆盖。

3. 发明申请

WO2004040668A3 FIELD EFFECT TRANSISTOR ASSEMBLY AND AN INTEGRATED CIRCUIT ARRAY 审中-公开
标题翻译：场效应晶体管布局和电路阵列
公开(公告)号：WO2004040668A3
公开(公告)日：2004-07-08
申请号：PCT/DE0303612
申请日：2003-10-30
申请人： INFINEON TECHNOLOGIES AG , GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
发明人： GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.
摘要翻译：本发明涉及一种场效应晶体管装置和一种电路阵列。场效应晶体管装置包括衬底，在衬底上具有第一源极/漏极区域的第一布线平面以及在第一布线平面上具有第二源极/漏极区域的第二布线平面。此外，场效应晶体管装置包含至少一个垂直纳米元件作为沟道区域，其布置在布线平面之间并耦合到两者。纳米元件至少部分地由导电材料包围的栅极区域，所述电绝缘材料作为纳米元件和所述导电材料之间的栅绝缘层提供。

4. 发明申请

WO2004040644A3 MEMORY CELL, MEMORY CELL ARRANGEMENT, STRUCTURING ARRANGEMENT AND METHOD FOR PRODUCTION OF A MEMORY CELL 审中-公开
标题翻译：存储单元中，存储器单元装置，纹理安排及其制造方法的存储单元
公开(公告)号：WO2004040644A3
公开(公告)日：2004-08-12
申请号：PCT/DE0303589
申请日：2003-10-29
申请人： INFINEON TECHNOLOGIES AG , GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
发明人： GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , H01L21/8239 , H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.
摘要翻译：本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。

5. 发明申请

WO02099845A3 ELECTRONIC CHIP AND ELECTRONIC CHIP ASSEMBLY 审中-公开
标题翻译：电子芯片和电子芯片配置
公开(公告)号：WO02099845A3
公开(公告)日：2003-08-21
申请号：PCT/DE0202026
申请日：2002-06-03
申请人： INFINEON TECHNOLOGIES AG , HOENLEIN WOLFGANG , KLOSE HELMUT , KREUPL FRANZ , SIMBUERGER WERNER
发明人： HOENLEIN WOLFGANG , KLOSE HELMUT , KREUPL FRANZ , SIMBUERGER WERNER
IPC分类号： H01L25/18 , H01L21/60 , H01L23/485 , H01L25/065 , H01L25/07 , H01L23/498 , C01B31/02 , H05K3/32 , H05K3/40
CPC分类号： H01L25/0657 , B82Y10/00 , B82Y30/00 , G01R31/2884 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/13019 , H01L2224/13023 , H01L2224/13078 , H01L2224/13099 , H01L2224/13193 , H01L2224/16145 , H01L2224/81065 , H01L2224/81097 , H01L2224/81191 , H01L2224/81424 , H01L2224/81447 , H01L2224/81801 , H01L2225/06513 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01072 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2924/00012 , H01L2224/05099 , H01L2224/05599 , H01L2224/05552
摘要： A plurality of nanotubes is mounted on at least one external metallic chip contact of the electronic chip for contacting said electronic chip with an additional electronic chip.
摘要翻译：在电子芯片中的至少一个外部片金属接触多个纳米管被应用于电子芯片与另外的电子芯片接触。

6. 发明申请

WO0250842A3 METHOD FOR READING OUT OR IN A STATUS FROM OR TO A FERROELECTRICAL TRANSISTOR OF A MEMORY CELL AND MEMORY MATRIX 审中-公开
标题翻译：用于从一个或一个存储器单元的铁电晶体读取和存储条件的方法以及存储器存储器
公开(公告)号：WO0250842A3
公开(公告)日：2002-12-27
申请号：PCT/DE0104785
申请日：2001-12-19
申请人： INFINEON TECHNOLOGIES AG , GOEBEL HOLGER , HOENIGSCHMID HEINZ , HOENLEIN WOLFGANG , HANEDER THOMAS , ULLMANN MARC
发明人： GOEBEL HOLGER , HOENIGSCHMID HEINZ , HOENLEIN WOLFGANG , HANEDER THOMAS , ULLMANN MARC
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , Y10S977/943
摘要： The status is read out from or stored in the ferroelectrical transistor. During the reading out or storing of the status, at least one further ferroelectrical transistor in the memory matrix is controlled such as to be operated in the depletion region thereof.
摘要翻译：该状态从铁电晶体管读出或存储在铁电晶体管中。在读取或存储状态期间，存储器矩阵中的至少一个另外的铁电晶体管被驱动，使得其在其耗尽区中操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式