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1. 发明申请

WO2016083332A1 METHOD FOR DIRECT BONDING OF SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：半导体衬底的直接接合方法
公开(公告)号：WO2016083332A1
公开(公告)日：2016-06-02
申请号：PCT/EP2015/077424
申请日：2015-11-24
申请人： IMEC VZW
发明人： KIM, Soon-Wook , PENG, Lan , VERDONCK, Patrick , MILLER, Robert , BEYER, Gerald , BEYNE, Eric
IPC分类号： H01L21/60 , H01L23/31
CPC分类号： H01L24/83 , H01L21/02065 , H01L21/02164 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/32 , H01L24/80 , H01L25/0657 , H01L2224/03452 , H01L2224/03462 , H01L2224/03616 , H01L2224/03845 , H01L2224/03848 , H01L2224/05568 , H01L2224/05573 , H01L2224/05576 , H01L2224/05686 , H01L2224/08121 , H01L2224/08145 , H01L2224/32501 , H01L2224/80097 , H01L2224/80201 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/83031 , H01L2224/83047 , H01L2224/83048 , H01L2224/83359 , H01L2924/00012 , H01L2924/0504 , H01L2924/00014 , H01L2924/20106 , H01L2924/2011
摘要： A method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometre. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre- treatments of the contact surfaces, and followed by a post- bond annealing step, at a temperature of less than or equal to 250°C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.
摘要翻译：描述通过直接接合将第一半导体衬底接合到第二半导体衬底的方法。这些基板都在其接触表面上设置有电介质层，接着是用于减小电介质层粗糙度的CMP步骤。然后将一层SiCN沉积到介电层上，随后是CMP步骤，其将SiCN层的粗糙度降低到十分之一纳米。然后将基板进行预结合退火步骤，然后通过直接接合进行粘合，可能之前是接触表面的一个或多个预处理，然后是后接合退火步骤，其温度低于或等于等于250°C。已经发现，即使在上述命名的退火温度下，粘合强度也是优异的，其比现有技术中已知的低。

2. 发明公开

EP4350760A1 A DEVICE AND SYSTEM FOR COOLING AN ELECTRONIC COMPONENT 审中-公开
公开(公告)号：EP4350760A1
公开(公告)日：2024-04-10
申请号：EP22199883.4
申请日：2022-10-05
申请人： IMEC VZW
发明人： CHERMAN, Vladimir , OPRINS, Herman , BEYNE, Eric
IPC分类号： H01L23/473 , H01L23/427
摘要： A cooling device (20) according to the invention is configured to be mounted in close proximity to an electronic component (2) that is to be cooled. The device comprises impingement channels (40) and return channels (41) for guiding a flow of cooling fluid towards and away from a cooled surface of the component. The device furthermore comprises a heat exchanger (22) and a pump (23), so that the flow cycle of a cooling fluid is fully confined within the device itself. The impingement channels (40), the return channels (41) and the heat exchanger (22) are integrated in a common housing (30), that comprises an inlet opening (24) and an outlet opening (25) for coupling the device to a refrigerant loop (10). The pump (23) may be a micropump mounted directly on the housing and coupled to inlet and outlet openings (35,36) in the housing (30). The invention is related to the device (20) as such and to a cooling system including a device according to the invention.

3. 发明公开

EP4016594A1 METHOD AND SYSTEM TO PRODUCE DIES FOR A WAFER RECONSTITUTION 审中-公开
公开(公告)号：EP4016594A1
公开(公告)日：2022-06-22
申请号：EP20214042.2
申请日：2020-12-15
申请人： Micledi Microdisplays BV , Imec VZW
发明人： BEYNE, Eric , REBIBIS, June Kenneth , MILLER, Robert , STEUDEL, Soeren , VERTOMMEN, Johan
IPC分类号： H01L21/66 , H01L21/78 , H01L25/00 , H01L33/00
摘要： A method is provided to produce dies for a wafer reconstitution. The method comprises steps of inspecting an epitaxial wafer (901) to detect one or more defects, overlaying a dicing scheme (902) on the epitaxial wafer (901) with the detected defects, classifying the dies in the dicing scheme (902) as good dies (903) or bad dies (904), and dicing the good dies (903) and transferring the good dies (903) onto a carrier wafer or a target wafer to wafer reconstitution.

4. 发明公开

EP3188230A1 LIQUID COOLING OF ELECTRONIC DEVICES 有权
标题翻译：电子器件的液体冷却
公开(公告)号：EP3188230A1
公开(公告)日：2017-07-05
申请号：EP15203217.3
申请日：2015-12-30
申请人： IMEC VZW
发明人： OPRINS, Herman , CHERMAN, Vladimir , BEYNE, Eric
IPC分类号： H01L23/473
摘要： A liquid cooling system for cooling an electronic device comprising a chip or a chip package comprising a chip is described. The liquid cooling system comprises an inlet plenum comprising a coolant feeding channel oriented substantially parallel with the plane of a main surface to be cooled of the chip and a plurality of inlet cooling channels fluidically connected to the coolant feeding channel and arranged vertically for impinging a liquid coolant directly on said main surface of the chip. The vertically oriented inlet cooling channels are substantially parallel to vertically oriented outlet cooling channels and are separated by a thermally isolating material. The liquid cooling system further comprises at least one cavity wherein a plurality of inlet and outlet cooling channels end. The cavity is arranged for allowing interaction between the liquid coolant and the main surface of the chip and thus comprises a heat transfer region.
摘要翻译：描述了用于冷却包括芯片或包括芯片的芯片封装的电子器件的液体冷却系统。该液体冷却系统包括进口增压室，该进口增压室包括与芯片的待冷却的主表面的平面基本平行取向的冷却剂进料通道以及流体连接至冷却剂进料通道并垂直布置以用于撞击液体的多个入口冷却通道直接在芯片的所述主表面上的冷却剂。垂直取向的入口冷却通道基本上平行于垂直取向的出口冷却通道并且被隔热材料隔开。液体冷却系统还包括至少一个空腔，其中多个入口和出口冷却通道终止。腔设置成允许液体冷却剂和芯片的主表面之间的相互作用，并且因此包括传热区域。

5. 发明授权

EP3188230B1 LIQUID COOLING OF ELECTRONIC DEVICES 有权
公开(公告)号：EP3188230B1
公开(公告)日：2020-09-02
申请号：EP15203217.3
申请日：2015-12-30
申请人： IMEC VZW
发明人： OPRINS, Herman , CHERMAN, Vladimir , BEYNE, Eric
IPC分类号： H01L23/473

6. 发明授权

EP2272087B1 METHOD FOR PROVIDING OXIDE LAYERS 有权
标题翻译：提供氧化物层的方法
公开(公告)号：EP2272087B1
公开(公告)日：2018-04-04
申请号：EP09738240.2
申请日：2009-04-30
申请人： IMEC VZW
发明人： SOUSSAN, Philippe , BEYNE, Eric , MULLER, Philippe
IPC分类号： H01L21/316
CPC分类号： H01L21/3167 , H01L21/02238 , H01L21/02258 , H01L21/31675
摘要： A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution.

7. 发明公开

EP3503160A1 A METHOD FOR FABRICATION OF AN ION TRAP 有权
公开(公告)号：EP3503160A1
公开(公告)日：2019-06-26
申请号：EP17210431.7
申请日：2017-12-22
申请人： IMEC vzw
发明人： HUYGHEBAERT, Cedric , BEYNE, Eric
IPC分类号： H01J49/00 , B81C1/00 , H01J49/42
摘要： According to an aspect of the present inventive concept there is provided a method for fabrication of an ion trap, the method comprising:
forming, on a first main surface of a first semiconductor wafer, a first electrode structure,
forming, on a first main surface of a second semiconductor wafer, a second electrode structure,
forming a first cavity part extending through the first semiconductor wafer from a second main surface thereof towards the first electrode structure,
forming a second cavity part extending through the second semiconductor wafer from a second main surface thereof towards the second electrode structure, and
bonding together the first semiconductor wafer and the second semiconductor wafer with the second main surface of the first semiconductor wafer facing the second main surface of the second semiconductor wafer and with the first cavity part and the second cavity part being aligned to together define an ion cavity, wherein the first electrode structure and the second electrode structure are arranged on opposite sides of the ion cavity.

8. 发明授权

EP2446478B1 BIOCOMPATIBLE PACKAGING 有权
公开(公告)号：EP2446478B1
公开(公告)日：2018-09-12
申请号：EP10727416.9
申请日：2010-06-25
申请人： IMEC VZW
发明人： OP DE BEECK, Maria , BEYNE, Eric , SOUSSAN, Philippe
IPC分类号： H01L23/00 , H01L23/31 , H01L29/06 , A61B5/00 , A61M5/142 , A61N1/372 , A61N1/375
CPC分类号： A61B5/686 , A61B5/6861 , A61B2562/0247 , A61B2562/028 , A61M5/14276 , A61M2205/0244 , A61M2205/8206 , A61N1/37205 , A61N1/375 , A61N1/3756 , H01L23/3114 , H01L24/48 , H01L2224/451 , H01L2224/48227 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

9. 发明公开

EP3799112A1 METHOD FOR DICING A SEMICONDUCTOR SUBSTRATE INTO A PLURALITY OF DIES 有权转让
公开(公告)号：EP3799112A1
公开(公告)日：2021-03-31
申请号：EP19200554.4
申请日：2019-09-30
申请人： Imec VZW
发明人： HOLSTEYNS, Frank , BEYNE, Eric , LORANT, Christophe , BRAUN, Simon
IPC分类号： H01L21/78 , H01L21/56
摘要： According to an aspect of the present inventive concept there is provided a method for dicing a semiconductor substrate (100) into a plurality of dies (170), wherein the semiconductor substrate having a front side (101) provided with a plurality of device areas (110), a back side (103), and a plurality of through substrate vias (130). The method comprises defining, from the front side (101) of the semiconductor substrate (100), at least one trench (140) to be formed between adjacent device areas (110a, 110b), forming the at least one trench (140), from the front side (101) of the semiconductor substrate (100), arranging a protective layer (150) on the front side (101) of the semiconductor substrate (100), thinning the semiconductor substrate (100) from the back side (103) to reduce the thickness (106) of the semiconductor substrate (100), processing the back side (103) of the semiconductor substrate 100 to form at least one contact (160), the contact (160) contacting at least one through substrate via (130), etching, from the back side (103) of the semiconductor substrate (100), through the minor portion (106b) of the thickness (106) of the semiconductor substrate (100) underneath the at least one trench (140), and dicing the semiconductor substrate (100) into the plurality of dies (170).

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