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1. 发明申请

WO2021058672A1 GRADIENT INDEX METAMATERIAL LENS FOR TERAHERTZ RADIATION 审中-公开
公开(公告)号：WO2021058672A1
公开(公告)日：2021-04-01
申请号：PCT/EP2020/076771
申请日：2020-09-24
申请人： IHP GMBH - INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS / LEIBNIZ-INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
发明人： CAO, Zhibo , KAYNAK, Mehmet , WIETSTRUCK, Matthias , STOCCHI, Matteo
IPC分类号： H01Q15/08 , H01Q15/10 , H01Q19/06
摘要： A lens (100) for terahertz radiation, which can be used in an antenna arrangement (400), comprises a cylindrical lens body made of silicon having a planar front surface and a planar back surface. The lens body has a front body region (30) which forms a silicon metamaterial with a relative permittivity that decreases in a lateral direction with increasing radial distance from a cylinder axis. A back body region (20) is immediately adjacent to the front body region and extends to the back surface. It consists of bulk silicon having a laterally constant relative permittivity. The front body region comprises holes that are distributed on the front surface in rings that are concentric with respect to the cylinder axis. The holes extend from the front surface to respective hole bottoms at an equal bottom level in a depth direction. The hole bottoms interface with the back body region.

2. 发明公开

EP3799209A1 GRADIENT INDEX METAMATERIAL LENS FOR TERAHERTZ RADIATION 审中-实审
公开(公告)号：EP3799209A1
公开(公告)日：2021-03-31
申请号：EP19199320.3
申请日：2019-09-24
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： CAO, Zhibo , KAYNAK, Mehmet , WIETSTRUCK, Matthias , STOCCHI, Matteo
IPC分类号： H01Q15/08 , H01Q15/10 , H01Q19/06
摘要： A lens (100) for terahertz radiation, which can be used in an antenna arrangement (400), comprises a cylindrical lens body made of silicon having a planar front surface and a planar back surface. The lens body has a front body region (30) which forms a silicon metamaterial with a relative permittivity that decreases in a lateral direction with increasing radial distance from a cylinder axis. A back body region (20) is immediately adjacent to the front body region and extends to the back surface. It consists of bulk silicon having a laterally constant relative permittivity. The front body region comprises holes that are distributed on the front surface in rings that are concentric with respect to the cylinder axis. The holes extend from the front surface to respective hole bottoms at an equal bottom level in a depth direction. The hole bottoms interface with the back body region.

3. 发明公开

EP3306654A1 METHOD FOR PREVENTING VERTICAL AND LATERAL INHOMOGENEITIES WHEN ETCHING THROUGH-SILICON VIAS 有权
标题翻译：通过硅通孔蚀刻时预防垂直和横向不均匀性的方法
公开(公告)号：EP3306654A1
公开(公告)日：2018-04-11
申请号：EP17193221.3
申请日：2017-09-26
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： WIETSTRUCK, Matthias , KAYNAK, Mehmet , KULSE, Philip , LISKER, Marco , MARSCHMEYER, Steffen , WOLANSKY, Dirk
IPC分类号： H01L21/768 , H01L23/48
摘要： A method for producing a semiconductor device, comprising the steps of: providing a silicon wafer having a plurality of raised portions of equal height on a first surface of the silicon wafer as a placeholder for through-silicon vias; depositing an etch stop layer on the first surface of the silicon wafer; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the surface of the etch stop layer; producing components on or in a second surface of the silicon wafer in a front-end-of-line process; etching a plurality of trenches into the silicon wafer using a masked etching process, proceeding from the second surface of the silicon wafer, each trench being formed at the respective location of one raised portion of the plurality of raised portions; depositing side wall insulation layers made of insulating material on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a back-end-of-line process for contacting the active components on the second surface of the silicon wafer; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the through-silicon vias by partially removing the etch stop layer.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在硅晶片的第一表面上提供具有相同高度的多个凸起部分的硅晶片作为硅通孔的占位符; 在硅晶片的第一表面上沉积蚀刻停止层; 平坦化蚀刻停止层的表面; 将第一载体晶片永久地结合在所述蚀刻停止层的表面上; 在线前处理中在硅晶片的第二表面上或其中生产组件; 使用掩模蚀刻工艺将多个沟槽蚀刻到硅晶片中，从硅晶片的第二表面开始，每个沟槽形成在多个凸起部分的一个凸起部分的相应位置处; 在沟槽的侧壁上沉积由绝缘材料制成的侧壁绝缘层; 通过用导电材料填充沟槽来形成硅通孔; 在后端处理工艺中产生导体路径堆叠，用于接触硅晶片的第二表面上的有源部件; 将第二载体晶片暂时接合到所述导体路径堆叠的表面上; 通过部分地去除所述蚀刻停止层来去除所述第一载体晶片并且暴露所述硅通孔。

4. 发明公开

EP4199072A3 FAN-OUT WAFER-LEVEL PACKAGE 审中-实审
公开(公告)号：EP4199072A3
公开(公告)日：2023-08-09
申请号：EP22213772.1
申请日：2022-12-15
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： WIETSTRUCK, Matthias , KAHMEN, Gerhard , KRÜGER, Patrick , VOSS, Thomas , STOCCHI, Matteo
IPC分类号： H01L23/36 , H01L21/60 , H01L23/66 , H01L21/683 , H01L25/10 , H01L21/56
摘要： Fan-out wafer-level package comprising at least one integrated circuit, an internal heat spreader thermally connected to the integrated circuit either directly or via an interface layer having a thickness in sub-µm range preferably in the range of 20 nm to 500 nm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.

5. 发明公开

EP4199072A2 FAN-OUT WAFER-LEVEL PACKAGE 审中-实审
公开(公告)号：EP4199072A2
公开(公告)日：2023-06-21
申请号：EP22213772.1
申请日：2022-12-15
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： WIETSTRUCK, Matthias , KAHMEN, Gerhard , KRÜGER, Patrick , VOSS, Thomas , STOCCHI, Matteo
IPC分类号： H01L23/36 , H01L21/60 , H01L23/66 , H01L21/683 , H01L25/10 , H01L21/56
摘要： Fan-out wafer-level package comprising at least one integrated circuit, an internal heat spreader thermally connected to the integrated circuit either directly or via an interface layer having a thickness in sub-µm range preferably in the range of 20 nm to 500 nm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.

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