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1. 发明授权

US08916975B2 Semiconductor memory device having pads 有权
标题翻译：具有衬垫的半导体存储器件
公开(公告)号：US08916975B2
公开(公告)日：2014-12-23
申请号：US12493617
申请日：2009-06-29
申请人： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： H01L23/48 , H01L23/52 , H01L23/528 , H01L23/00
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
摘要翻译：半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。这对数据线被布置为彼此相邻并且接收一对差分数据信号。电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。

2. 发明授权

US08810274B2 On-die termination circuit 有权
标题翻译：片上终端电路
公开(公告)号：US08810274B2
公开(公告)日：2014-08-19
申请号：US13657123
申请日：2012-10-22
申请人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K17/16
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

3. 发明授权

US08047454B2 Structure for fixing reducer for sprinkler in side wall 有权
标题翻译：侧壁喷淋头固定减速机结构
公开(公告)号：US08047454B2
公开(公告)日：2011-11-01
申请号：US12460554
申请日：2009-07-20
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： B05B15/10
CPC分类号： F16L3/18 , A62C31/28 , A62C35/68
摘要： The present invention relates to a structure for fixing a reducer for a sprinkler in a side wall, and more particularly, to a structure for fixing a reducer for a sprinkler for side wall construction, in which since the reducer can easily adjust a distance from the side wall in the horizontal direction, a connection work between the reducer and the sprinkler head for the side wall construction connected to the reducer can be conveniently performed.
摘要翻译：本发明涉及一种用于在侧壁中固定用于喷洒器的减速器的结构，更具体地，涉及用于固定用于侧壁结构的喷洒器的减速器的结构，其中由于减速器可以容易地调节距离侧壁在水平方向上，可以方便地进行与还原器连接的侧壁结构的减速器和喷头之间的连接作业。

4. 发明授权

US07915939B2 Duty cycle correction apparatus and semiconductor integrated circuit having the same 有权
标题翻译：占空比校正装置和具有该占空比校正装置的半导体集成电路
公开(公告)号：US07915939B2
公开(公告)日：2011-03-29
申请号：US12407727
申请日：2009-03-19
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/0814
摘要： A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.
摘要翻译：占空比校正装置包括：固定延迟单元，被配置为将固定延迟时间设置为DLL时钟信号，并产生延迟上升时钟信号; 可变延迟单元，被配置为响应于控制信号延迟所述DLL时钟信号并产生延迟下降时钟信号; 占空比校正单元，被配置为产生与延迟上升时钟信号和延迟下降时钟信号的边沿定时一致的校正上升时钟信号和校正下降时钟信号; 以及延迟控制单元，被配置为检测所述校正上升时钟信号和所述校正下降时钟信号的占空比，并产生所述控制信号。

5. 发明授权

US07843481B2 Light scanning device capable of producing non-coplanar scanning lines 有权
标题翻译：能够产生非共面扫描线的光扫描装置
公开(公告)号：US07843481B2
公开(公告)日：2010-11-30
申请号：US12252856
申请日：2008-10-16
申请人： Hyung Soo Kim , Sun Min Kin
发明人： Hyung Soo Kim , Sun Min Kin
IPC分类号： B41J15/14 , B41J27/00
CPC分类号： G03G15/326 , B41J2/473 , G03G15/0435 , H04N1/00525
摘要： An image forming apparatus having improved arrangement of photosensitive members and configuration of a light scanning device to enable size reduction is described. The image forming apparatus includes a plurality of photosensitive members, a light scanning device to irradiate light beams to the plurality of photosensitive members, so as to form electrostatic latent images on the photosensitive members, a plurality of developers to supply a developing agent to the photosensitive members, so as to form visible images on the photosensitive members, and a transfer drum disposed in contact with the photosensitive members and used to transfer the visible images such that the visible images overlap one another. Scanning lines, which are formed on the plurality of photosensitive members, respectively, by the light scanning device, are arranged in at least two different planes.
摘要翻译：描述了一种具有改进的感光构件布置的图像形成装置和光扫描装置的结构以使尺寸减小。图像形成装置包括多个感光构件，用于将光束照射到多个感光构件的光扫描装置，以便在感光构件上形成静电潜像，多个显影剂将显影剂供应到感光体以便在感光构件上形成可见图像，以及与感光构件接触设置的转印鼓，用于传送可见图像使得可视图像彼此重叠。分别由光扫描装置形成在多个感光构件上的扫描线被布置在至少两个不同的平面中。

6. 发明申请

US20100060332A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100060332A1
公开(公告)日：2010-03-11
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

7. 发明申请

US20090206901A1 DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION 失效
标题翻译：具有降低电流消耗的占空比校正电路
公开(公告)号：US20090206901A1
公开(公告)日：2009-08-20
申请号：US12333193
申请日：2008-12-11
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.
摘要翻译：一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

8. 发明申请

US20090002040A1 DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的DLL电路
公开(公告)号：US20090002040A1
公开(公告)日：2009-01-01
申请号：US11964824
申请日：2007-12-27
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.
摘要翻译：一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

9. 发明申请

US20080237407A1 Structure for fixing reducer for sprinkler in side wall 有权
公开(公告)号：US20080237407A1
公开(公告)日：2008-10-02
申请号：US11731693
申请日：2007-03-30
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： B05B3/02 , F16L3/08
CPC分类号： F16L3/18 , A62C31/28 , A62C35/68
摘要： Provided is a structure for fixing a reducer for a sprinkler in side wall construction, which includes a bracket, a reducer, and an adjusting bolt. The bracket includes a first transverse portion, a first longitudinal portion, a second transverse portion, and a second longitudinal portion. The first transverse portion includes an elongated hole formed in order to be fixed on a ceiling with at least one fixing member. The first longitudinal portion is bent perpendicularly with the first transverse portion at one end of the first transverse portion. The second transverse portion is formed in parallel with the first transverse portion on the bottom of the first longitudinal portion, in which a rail hole is formed in the plate surface thereof. The second longitudinal portion is formed in parallel with the first longitudinal portion at the end part of the second transverse portion, in which a screw tap is formed in the plate surface thereof and simultaneously a through-hole is formed in one side of the rail hole. The reducer includes a rail block and a plate. The rail block is formed into a linear type tubular body with one end of which a flexible tube is combined and with the other end of which the head of the sprinkler for side wall construction is combined. The rail block is arranged in parallel with the second transverse portion at the lower portion of the second transverse portion, and is protruded from the upper-center portion of the reducer, in which sliding grooves formed in the rail block are engaged with a rail hole formed at the second transverse portion to thereby allow the rail block to move in the form of a rail. The plate is arranged in parallel with the second longitudinal portion at the location spaced from the rail block, in which a through-hole is formed in the plate surface. The adjusting bolt is inserted into the through-hole of the plate and is screwed into a screw tap of the second longitudinal portion, to thus enable the reducer to reciprocate in the direction which is in parallel with the second transverse portion during forward and backward rotation. In this way, since the reducer is configured to easily adjust a distance from the side wall in the vertical direction as well as in the horizontal direction, a connection work between the reducer and the sprinkler head for the side wall construction connected to the reducer can be conveniently performed, and the intensity of the reducer fixing structure can be reinforced.

10. 发明申请

US20080068058A1 PLL circuit having loop filter and method of driving the same 有权
标题翻译：具有环路滤波器的PLL电路及其驱动方法
公开(公告)号：US20080068058A1
公开(公告)日：2008-03-20
申请号：US11822103
申请日：2007-07-02
申请人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/085 , H03L7/08
CPC分类号： H03L7/093 , H03L7/10
摘要： A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.
摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，并产生上拉控制信号和下拉控制信号。环路滤波器根据上拉和下拉控制信号抽取电压，对泵浦电压进行滤波，并输出一个控制电压。压控振荡器接收控制信号并振荡输出时钟。时钟分频器以预定速率分频输出时钟的频率，以产生反馈时钟。在PLL电路中，环路滤波器包括用于补偿变化的补偿器。

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