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    • 3. 发明授权
    • Bus interface logic integrated circuit
    • 总线接口逻辑集成电路
    • US5521537A
    • 1996-05-28
    • US363645
    • 1994-12-22
    • Kyoung H. Kim
    • Kyoung H. Kim
    • G06F13/36G06F13/38H03K19/0175
    • G06F13/385
    • A bus interface logic integrated circuit having a function of bus interfacing a system bus with a higher-order module, including a programmable chip connected between the system bus and the higher-order module and adapted to bus interface the system bus and the higher-order module with each other, the programmable chip initiating transmission and receipt of data under a control of the higher-order module. The programmable chip includes input/output units for selecting data input and output between the system bus and the higher-order module, a part of the input/output units being connected to the system bus and the other input/output unit part being connected to the higher-order module, and a combination logic unit for combining parameters generated for the transmission and receipt of data between each of the system bus-side input/output units and each corresponding one of the higher-order module-side input/output units and outputting a value required for the transmission and receipt of data on the basis of the result of the combination.
    • 一种总线接口逻辑集成电路,具有总线将系统总线与高阶模块接口的功能,该系统总线包括连接在系统总线与高阶模块之间的可编程芯片,并适用于总线接口系统总线和高阶模块 模块,可编程芯片在高阶模块的控制下启动传输和接收数据。 可编程芯片包括用于选择系统总线和高阶模块之间的数据输入和输出的输入/输出单元,一部分输入/输出单元连接到系统总线,另一个输入/输出单元部分连接到 高阶模块和组合逻辑单元,用于组合为每个系统总线侧输入/输出单元与高阶模块侧输入/输出单元中的每一个之间的数据的发送和接收而生成的参数 并根据组合的结果输出发送和接收数据所需的值。