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    • 8. 发明申请
    • Thin film transistor array panel
    • 薄膜晶体管阵列面板
    • US20060033871A1
    • 2006-02-16
    • US11254134
    • 2005-10-18
    • Hyun-Wuk KimJae-Jin LyuYoon-Sung UmChang-Hun Lee
    • Hyun-Wuk KimJae-Jin LyuYoon-Sung UmChang-Hun Lee
    • G02F1/1343
    • G02F1/134309G02F1/136286G02F2001/134345
    • A thin film transistor array panel according to one embodiment of the invention comprises: first, second, and third pixel electrodes arranged sequentially, the second pixel electrode including first and second sub-pixel electrodes, the second pixel electrode occupying an area comprising a first area and a second area that is disposed closer to the third pixel electrode than the first area; first, second, and third thin film transistors connected to the first, the second, and the third pixel electrodes, respectively; first, second, and third gate lines connected to the first, the second, and the third thin film transistors, respectively; and a data line connected to the first, the second, and the third thin film transistors, wherein the second sub-pixel electrode is capacitively coupled to the third pixel electrode, and the second sub-pixel electrode is present in both the first and the second areas.
    • 根据本发明的一个实施例的薄膜晶体管阵列面板包括:顺序布置的第一,第二和第三像素电极,第二像素电极包括第一和第二子像素电极,第二像素电极占据包括第一区域 以及比所述第一区域更靠近所述第三像素电极设置的第二区域; 分别连接到第一,第二和第三像素电极的第一,第二和第三薄膜晶体管; 分别连接到第一,第二和第三薄膜晶体管的第一,第二和第三栅极线; 以及连接到第一,第二和第三薄膜晶体管的数据线,其中第二子像素电极电容耦合到第三像素电极,并且第二子像素电极存在于第一和第三薄膜晶体管的第一和第三薄膜晶体管中, 第二区。