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    • 3. 发明授权
    • Voltage reference circuit and current reference circuit using vertical bipolar junction transistor implemented by deep n-well CMOS process
    • 采用深n阱CMOS工艺实现的垂直双极结型晶体管的参考电压和电流参考电路
    • US07564298B2
    • 2009-07-21
    • US11608279
    • 2006-12-08
    • Hyun-Won MunIl-Ku NamSang-Yeob LeeMin-Kyu Je
    • Hyun-Won MunIl-Ku NamSang-Yeob LeeMin-Kyu Je
    • G05F1/10
    • G05F3/30
    • A voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, wherein the voltage reference circuit generates a constant reference voltage regardless of temperature and includes an amplifier element having a positive input terminal and a negative input terminal, a first transistor, and a second transistor. The first transistor is electrically connected to the positive input terminal and the second transistor is electrically connected to the negative input terminal. Each of the first and second transistors is a vertical BJT implemented by a deep N-well CMOS process, and the reference voltage is calculated by adding a base-emitter voltage of one of the first and second transistors to a value obtained by multiplying a thermal voltage by a predetermined factor. Accordingly, circuits having better reproducibility, uniformity, and device matching than circuits that use a lateral NPN/PNP device or substrate NPN/PNP device manufactured using a CMOS process are provided.
    • 使用通过深N阱互补金属氧化物半导体(CMOS)工艺实现的垂直双极结型晶体管(BJT)的电压参考电路和电流参考电路,其中所述电压参考电路产生恒定的参考电压,而不管温度如何,并且包括 具有正输入端和负输入端的放大器元件,第一晶体管和第二晶体管。 第一晶体管电连接到正输入端,第二晶体管电连接到负输入端。 第一晶体管和第二晶体管中的每一个是通过深N阱CMOS工艺实现的垂直BJT,并且通过将第一和第二晶体管中的一个晶体管的基极 - 发射极电压相加到通过将热 电压达预定因子。 因此,提供了具有比使用使用CMOS工艺制造的侧面NPN / PNP器件或衬底NPN / PNP器件的电路更好的再现性,均匀性和器件匹配的电路。
    • 4. 发明申请
    • SEMICONDUCTOR CIRCUITS USING VERTICAL BIPOLAR JUNCTION TRANSISTOR
    • 使用垂直双极晶体管晶体管的半导体电路
    • US20080106304A1
    • 2008-05-08
    • US11560452
    • 2006-11-16
    • Hyun-Won MunIl-Ku Nam
    • Hyun-Won MunIl-Ku Nam
    • G01R19/00
    • H03F3/165
    • An amplifier circuit includes: an amplification transistor, which is connected to an input node and an output node, amplifying an input signal and generating an output signal; and a load connected between the output node and a predetermined power supply node, wherein the amplification transistor is a vertical bipolar junction transistor. A variable gain amplifier circuit includes: a voltage converter converting a control voltage and outputting a converted control voltage; and an amplification transistor receiving the converted control signal from the voltage converter and amplifying an input signal to output an output signal whose gain is proportional to the control voltage, wherein the amplification transistor is a vertical bipolar junction transistor. A single pole log-domain circuit includes: a first transistor receiving an input current; a second transistor having a base terminal connected to a base terminal of the first transistor; a third transistor having an emitter terminal connected to an emitter terminal of the second transistor; and a fourth transistor having a base terminal connected to a base terminal of the third transistor, wherein each of the first through fourth transistors is a vertical BJT.
    • 放大电路包括:放大晶体管,其连接到输入节点和输出节点,放大输入信号并产生输出信号; 以及连接在所述输出节点和预定电源节点之间的负载,其中所述放大晶体管是垂直双极结型晶体管。 可变增益放大器电路包括:转换控制电压并输出转换的控制电压的电压转换器; 以及放大晶体管,其接收来自所述电压转换器的转换后的控制信号,并放大输入信号以输出其增益与所述控制电压成比例的输出信号,其中所述放大晶体管为垂直双极结型晶体管。 单极对数域电路包括:接收输入电流的第一晶体管; 第二晶体管,其具有连接到所述第一晶体管的基极端子的基极; 第三晶体管,其发射极端子连接到第二晶体管的发射极端子; 以及具有连接到所述第三晶体管的基极端子的基极端子的第四晶体管,其中所述第一至第四晶体管中的每一个是垂直BJT。
    • 7. 发明授权
    • Programmable variable gain amplifier and RF receiver including the same
    • 可编程可变增益放大器和射频接收器包括相同
    • US07860468B2
    • 2010-12-28
    • US11933504
    • 2007-11-01
    • Il-Ku NamByeong-Ha ParkJong-Dae BaeJung-Wook HeoHo-Jung JuHyun-Won MunJeong-Hyun Choi
    • Il-Ku NamByeong-Ha ParkJong-Dae BaeJung-Wook HeoHo-Jung JuHyun-Won MunJeong-Hyun Choi
    • H04B1/04H04B1/06
    • H03F3/19H03F1/32H03F2200/294H03G1/0029H03G1/0088
    • A programmable variable gain amplifier includes at least three amplifiers. A first amplifier is configured to amplify an input signal. A second amplifier, which includes a programmable output load stage, is configured to receive an output signal from the first amplifier and to output a first differential output signal. The output load stage includes multiple first switches and multiple first diode-connected transistors that are open-circuited or short-circuited by the first switches. A third amplifier, which includes a programmable current mirror input stage, is configured to receive the first differential output signal from the second amplifier through the current mirror input stage and to output a second differential output signal. The current mirror input stage includes multiple second switches and multiple second transistors that are open-circuited or short-circuited by the plurality of second switches. The second transistors respectively form current mirrors with the first diode-connected transistors corresponding to the second transistors.
    • 可编程可变增益放大器包括至少三个放大器。 第一放大器被配置为放大输入信号。 包括可编程输出负载级的第二放大器被配置为从第一放大器接收输出信号并输出​​第一差分输出信号。 输出负载级包括由第一开关断开或短路的多个第一开关和多个第一二极管连接的晶体管。 包括可编程电流镜输入级的第三放大器被配置为通过电流镜输入级从第二放大器接收第一差分输出信号并输出​​第二差分输出信号。 电流反射镜输入级包括多个第二开关和由多个第二开关断路或短路的多个第二晶体管。 第二晶体管分别形成与第二晶体管对应的第一二极管连接的晶体管的电流镜。
    • 8. 发明申请
    • VOLTAGE REFERENCE CIRCUIT AND CURRENT REFERENCE CIRCUIT USING VERTICAL BIPOLAR JUNCTION TRANSISTOR IMPLEMENTED BY DEEP N-WELL CMOS PROCESS
    • 使用深埋N-CMOS CMOS工艺实现的垂直双极晶体管的电压参考电路和电流参考电路
    • US20070182478A1
    • 2007-08-09
    • US11608279
    • 2006-12-08
    • Hyun-Won MunIl-Ku NamSang-Yeob LeeMin-Kyu Je
    • Hyun-Won MunIl-Ku NamSang-Yeob LeeMin-Kyu Je
    • G05F1/10
    • G05F3/30
    • A voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, wherein the voltage reference circuit generates a constant reference voltage regardless of temperature and includes an amplifier element having a positive input terminal and a negative input terminal, a first transistor, and a second transistor. The first transistor is electrically connected to the positive input terminal and the second transistor is electrically connected to the negative input terminal. Each of the first and second transistors is a vertical BJT implemented by a deep N-well CMOS process, and the reference voltage is calculated by adding a base-emitter voltage of one of the first and second transistors to a value obtained by multiplying a thermal voltage by a predetermined factor. Accordingly, circuits having better reproducibility, uniformity, and device matching than circuits that use a lateral NPN/PNP device or substrate NPN/PNP device manufactured using a CMOS process are provided.
    • 使用通过深N阱互补金属氧化物半导体(CMOS)工艺实现的垂直双极结型晶体管(BJT)的电压参考电路和电流参考电路,其中所述电压参考电路产生恒定的参考电压,而不管温度如何,并且包括 具有正输入端和负输入端的放大器元件,第一晶体管和第二晶体管。 第一晶体管电连接到正输入端,第二晶体管电连接到负输入端。 第一晶体管和第二晶体管中的每一个是通过深N阱CMOS工艺实现的垂直BJT,并且通过将第一和第二晶体管中的一个晶体管的基极 - 发射极电压相加到通过将热 电压达预定因子。 因此,提供了具有比使用使用CMOS工艺制造的侧面NPN / PNP器件或衬底NPN / PNP器件的电路更好的再现性,均匀性和器件匹配的电路。