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1. 发明申请

US20110157129A1 SOURCE DRIVER CIRCUIT OF LIQUID CRYSTAL DISPLAY DEVICE 审中-公开
标题翻译：液晶显示装置的源驱动电路
公开(公告)号：US20110157129A1
公开(公告)日：2011-06-30
申请号：US12974584
申请日：2010-12-21
申请人： Hyun-Min SONG , Young-Suk Son , Ji-Hum Kim , Joon-Ho Na
发明人： Hyun-Min SONG , Young-Suk Son , Ji-Hum Kim , Joon-Ho Na
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/36 , G09G3/3685 , G09G3/3696 , G09G2300/0408 , G09G2320/0252
摘要： A source driver circuit of a liquid crystal display device including a gamma buffer. The gamma buffer includes a differential amplification section configured to differentially amplify an input signal; a current mirror section configured to operate as a current mirror; an enable section configured to convert the differential amplification section from a standby mode to an enable mode by a bias voltage; a power drop speed improvement section configured to respectively connect drains of the two PMOS transistors of the current mirror section and drains of the two NMOS transistors of the differential amplification section through two diode coupling type MOS transistors, and shorten a recovery time after a power drop; and an output section configured to be determined in a bias level thereof by the bias voltage and generate an output voltage according to a voltage of a downstream node on one side of the current mirror section.
摘要翻译：一种包括伽马缓冲器的液晶显示装置的源极驱动电路。伽马缓冲器包括被配置为差分放大输入信号的差分放大部分; 配置为作为电流镜操作的电流镜部; 使能部分，被配置为通过偏置电压将差分放大部分从待机模式转换为使能模式; 功率下降速度改善部分，被配置为通过两个二极管耦合型MOS晶体管分别连接电流镜部分的两个PMOS晶体管的漏极和差分放大部分的两个NMOS晶体管的漏极，并且在掉电之后缩短恢复时间 ; 以及输出部，被配置为通过偏置电压在其偏置电平中确定，并且根据当前镜部的一侧上的下游节点的电压产生输出电压。

2. 发明申请

US20110128273A1 DISPLAY PANEL DRIVING CIRCUIT AND DRIVING METHOD USING THE SAME 审中-公开
标题翻译：显示面板驱动电路及使用其的驱动方法
公开(公告)号：US20110128273A1
公开(公告)日：2011-06-02
申请号：US12951745
申请日：2010-11-22
申请人： Hyun-Min SONG , Ji-Hun Kim , Young-Bok Kim , Joon-Ho Na
发明人： Hyun-Min SONG , Ji-Hun Kim , Young-Bok Kim , Joon-Ho Na
IPC分类号： G09G5/00
CPC分类号： G09G3/3685 , G09G3/3614 , G09G2310/0248 , G09G2310/0291 , G09G2310/0297 , G09G2330/023
摘要： A display panel driving circuit includes: N number of buffers (N is an integer no less than 1) configured to buffer data voltages and enable or disable supply of buffered signals in response to a charge sharing control signal; and N number of output multiplexers each configured to receive outputs of two adjacent buffers among outputs of the N number of buffers and transfer the output of one buffer or the outputs of the two buffers to a corresponding one of data lines in response to the charge sharing control signal.
摘要翻译：显示面板驱动电路包括：N个缓冲器（N是不小于1的整数），其被配置为缓冲数据电压，并响应于电荷共享控制信号启用或禁止提供缓冲信号; N个输出多路复用器，每个被配置为在N个缓冲器的输出中接收两个相邻缓冲器的输出，并且响应于电荷共享将一个缓冲器的输出或两个缓冲器的输出传送到相应的数据线控制信号。

3. 发明申请

US20120133631A1 SOURCE DRIVER OUTPUT CIRCUIT OF FLAT PANEL DISPLAY DEVICE 审中-公开
标题翻译：平板显示设备的源驱动器输出电路
公开(公告)号：US20120133631A1
公开(公告)日：2012-05-31
申请号：US13301101
申请日：2011-11-21
申请人： Hun-Yong Lim , Ji-Hun Kim , Hyun-Min Song , Sang-Woo Kim , Joon-Ho Na
发明人： Hun-Yong Lim , Ji-Hun Kim , Hyun-Min Song , Sang-Woo Kim , Joon-Ho Na
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G2310/0248
摘要： In a source driver output circuit of a flat panel display device, first and second latch units receive image data and store the received image data. A D/A converter converts the image data into a data voltage. An output buffer unit outputs the data voltage to a data line. A switching control unit decides whether or not the data voltages of two image data of the same channel among image data of horizontal lines adjacent to each other, stored in the first and second latch units, belong to the same grayscale voltage range, and outputs a switching control signal based on the decided result. A multiplexer unit selects a pre-charge voltage in response to the switching control signal or continuously maintains a connection state between a corresponding channel of the output buffer unit and the corresponding data line.
摘要翻译：在平板显示装置的源极驱动器输出电路中，第一和第二锁存单元接收图像数据并存储所接收的图像数据。 D / A转换器将图像数据转换成数据电压。输出缓冲单元将数据电压输出到数据线。切换控制单元判定存储在第一和第二锁存单元中的彼此相邻的水平线的图像数据中的相同信道的两个图像数据的数据电压是否属于相同的灰度级电压范围，并输出根据决定的结果切换控制信号。复用器单元响应于切换控制信号选择预充电电压，或者连续地保持输出缓冲器单元的相应通道与相应数据线之间的连接状态。

4. 发明授权

US08933919B2 Liquid crystal panel driving circuit for display stabilization 有权
标题翻译：液晶面板驱动电路，用于显示稳定
公开(公告)号：US08933919B2
公开(公告)日：2015-01-13
申请号：US13461317
申请日：2012-05-01
申请人： Yeong-Joon Son , Ji-Hun Kim , Sang-Min Lee , Joon-Ho Na , Hae-Won Lee
发明人： Yeong-Joon Son , Ji-Hun Kim , Sang-Min Lee , Joon-Ho Na , Hae-Won Lee
IPC分类号： G06F3/038 , G09G3/36
CPC分类号： G09G3/3685 , G09G2310/0248 , G09G2310/0297 , G09G2330/026 , G09G2330/027
摘要： Disclosed is a liquid crystal panel driving circuit of display stabilization, including: a plurality of output buffers buffering data voltage and supplying or cutting off the buffered data voltage to or from each of the plurality of data lines; an output MUX switch receiving outputs from two adjacent output buffers of the plurality of output buffers and transferring one of the two outputs to the plurality of data lines; a garbage switch connecting each of the plurality of data lines to a ground terminal; and a power on sensor or a power off sensor generating a power on or off reset signal in response to a turn on/off of a power supply voltage, wherein the output MUX switch is turned-off and the charge share switch and the garbage switch are turned-on, in response to the power on reset signal or the power off reset signal.
摘要翻译：公开了一种显示稳定化的液晶面板驱动电路，包括：缓冲数据电压的多个输出缓冲器，并向多个数据线中的每个数据线提供缓冲的数据电压或从其中切出缓冲的数据电压; 输出MUX开关，其接收来自所述多个输出缓冲器的两个相邻输出缓冲器的输出，并将所述两个输出中的一个传送到所述多条数据线; 将所述多条数据线中的每一条连接到接地端的垃圾开关; 以及响应于电源电压的接通/断开而产生电源接通/断开复位信号的电源接通传感器或断电传感器，其中所述输出MUX开关断开，并且所述电荷共享开关和所述垃圾开关响应于上电复位信号或断电复位信号而导通。

5. 发明申请

US20100141687A1 METHOD OF ARRANGING GAMMA BUFFERS AND FLAT PANEL DISPLAY APPLYING THE METHOD 审中-公开
标题翻译：应用该方法的装置缓冲器和平板显示器的方法
公开(公告)号：US20100141687A1
公开(公告)日：2010-06-10
申请号：US12594794
申请日：2008-03-26
申请人： Dae-Keun Han , Dae-Seong Kim , Joon-Ho Na , Hong-Hee Son , Hyun-Ho Cho , Hyung-Seog Oh
发明人： Dae-Keun Han , Dae-Seong Kim , Joon-Ho Na , Hong-Hee Son , Hyun-Ho Cho , Hyung-Seog Oh
IPC分类号： G09G5/10
CPC分类号： G09G3/2007 , G09G2310/0275 , G09G2320/0276 , G09G2320/041
摘要： Provided are a method of arranging gamma buffers capable of decreasing a Kelvin of a source driver included in a flat panel display and minimizing a temperature deviation between source drivers, and the flat panel display applying the method. The method of arranging a plurality of gamma buffers which are arranged in one or more source drivers to output corresponding gamma voltages, includes a step of calculating power consumptions of the gamma buffers, wherein the method further comprises one or more steps of: changing tab points of the gamma buffers by using the calculated power consumptions of the gamma buffers; and changing positions of the gamma buffers by using the calculated power consumptions of the gamma buffers.
摘要翻译：提供了一种布置能够降低平板显示器中包括的源极驱动器的开尔文并使源极驱动器之间的温度偏差最小化的应用该方法的平板显示器的方法。布置在一个或多个源驱动器中以输出相应伽马电压的多个伽马缓冲器的方法包括计算伽马缓冲器的功耗的步骤，其中该方法还包括一个或多个步骤：改变标记点的γ缓冲器的功率消耗; 以及通过使用计算出的伽马缓冲器的功率消耗来改变伽马缓冲器的位置。

6. 发明授权

US09129551B2 Driving circuit of display apparatus and driving chip 有权
标题翻译：显示设备和驱动芯片的驱动电路
公开(公告)号：US09129551B2
公开(公告)日：2015-09-08
申请号：US13422961
申请日：2012-03-16
申请人： Young-Gi Kim , Na-Ra Hong , Hye-Lan Kim , Joon-Ho Na
发明人： Young-Gi Kim , Na-Ra Hong , Hye-Lan Kim , Joon-Ho Na
IPC分类号： G06F3/038 , G09G3/20
CPC分类号： G09G3/20 , G09G2310/0275 , G09G2330/026 , G09G2370/08
摘要： Disclosed are a driving circuit of a display apparatus and a driving chip, which shuts off the output of image data, in a display apparatus in which a plurality of driving chips is connected to each other in a daisy chain method to correspond to a single display panel, when serial communication of the driving chips is not completed successfully, or when any one of the driving chips is not operated normally, thereby preventing an abnormal screen from being displayed.
摘要翻译：公开了一种显示装置和驱动芯片的驱动电路，其在多个驱动芯片以菊花链方式彼此连接以对应于单个显示器的显示装置中切断图像数据的输出当驱动芯片的串行通信未成功完成时，或者当任何一个驱动芯片不正常地操作时，从而防止显示异常屏幕。

7. 发明授权

US08258631B2 Pad layout structure of semiconductor chip 有权
标题翻译：垫片布局结构的半导体芯片
公开(公告)号：US08258631B2
公开(公告)日：2012-09-04
申请号：US12600901
申请日：2007-12-17
申请人： Dae-Keun Han , Dae-Seong Kim , Joon-Ho Na
发明人： Dae-Keun Han , Dae-Seong Kim , Joon-Ho Na
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/73
CPC分类号： H01L24/06 , H01L23/544 , H01L24/86 , H01L2223/54426 , H01L2224/05553 , H01L2224/05599 , H01L2224/0603 , H01L2224/06051 , H01L2224/45144 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2224/48
摘要： Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.
摘要翻译：提供一种半导体芯片的焊盘布局结构，其能够防止在带状载体封装（TCP）中封装具有高纵横比的半导体芯片时的引线断裂问题。在半导体芯片的焊盘布局结构中，多个焊盘沿着半导体芯片的上部，下部，左侧和右侧以高纵横比布置，并且布置在左侧和右侧的焊盘的纵向宽度和横向布置在上侧和下侧的两个边缘处的垫的宽度大于布置在上侧和下侧中心处的垫的横向宽度。

8. 发明授权

US6088284A Memory chip having multiple input/output system 有权
标题翻译：具有多个输入/输出系统的存储芯片
公开(公告)号：US6088284A
公开(公告)日：2000-07-11
申请号：US239780
申请日：1999-01-29
申请人： Jung-Yong Lee , Joon-Ho Na
发明人： Jung-Yong Lee , Joon-Ho Na
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1006
摘要： A memory chip having a multiple input/output system enables a memory to have a .times.n, .times.2n or .times.4n I/O system through a simple fuse mask process by using a single memory chip and reduces the consumption of a cell current while having a memory capacity which is the same as in the .times.n or .times.2n I/O system of the conventional art. The multiple input/output memory chip according to the present invention includes a block selecting unit for receiving a source voltage or a column address lowest bit and thereby selectively activating a first block selection signal or a second block selection signal, a column control unit for receiving a source voltage or a column address lowest bit and thereby selectively activating a first column control signal or a second column control signal, a first bank for simultaneously reading or writing n-bit or 2n-bit data in accordance with the first or second column control signal and the first block selection signal, a second bank for simultaneously reading or writing n-bit or 2n-bit data in accordance with the first or second column control signal and the second block selection signal, and a data bus which is connected with first to third fuses and thereby dividable up to four parts.
摘要翻译：具有多重输入/输出系统的存储器芯片使得存储器能够通过使用单个存储器芯片的简单熔丝掩模处理来具有xn，x2n或x4n I / O系统，并且在具有存储器容量的同时减少电池电流的消耗这与传统技术的xn或x2n I / O系统相同。根据本发明的多输入/输出存储器芯片包括：块选择单元，用于接收源电压或列地址最低位，从而选择性地激活第一块选择信号或第二块选择信号;列控制单元，用于接收源电压或列地址最低位，从而选择性地激活第一列控制信号或第二列控制信号，第一存储体，用于根据第一或第二列控制同时读取或写入n位或2n位数据信号和第一块选择信号，第二组，用于根据第一或第二列控制信号和第二块选择信号同时读取或写入n位或2n位数据，以及数据总线，其与第一块到第三个保险丝，从而可以分配多达四个部分。

9. 发明授权

US5986963A Write control driver circuit 失效
标题翻译：写控制驱动电路
公开(公告)号：US5986963A
公开(公告)日：1999-11-16
申请号：US61034
申请日：1998-04-16
申请人： Joon-Ho Na
发明人： Joon-Ho Na
IPC分类号： G11C11/41 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/417 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1078
摘要： A write control driver circuit writes a data in a high-speed semiconductor chip by obtaining an earlier enabling time of a write control signal. The circuit includes a first logic circuit unit that outputs a first pulse signal of an address transition detection signal based on an input write enable signal, a second pulse signal of an address transition detection signal generated after the first pulse signal, and a delay control signal in which the first pulse signal is removed when the first and second pulse signals are inputted thereto. A second logic circuit unit that receives the delay control signal and a coding signal and output a write control signal.
摘要翻译：写控制驱动器电路通过获得写入控制信号的较早使用时间将数据写入高速半导体芯片。该电路包括第一逻辑电路单元，其基于输入写入使能信号输出地址转换检测信号的第一脉冲信号，在第一脉冲信号之后产生的地址转换检测信号的第二脉冲信号和延迟控制信号其中当输入第一和第二脉冲信号时第一脉冲信号被去除。第二逻辑电路单元，其接收延迟控制信号和编码信号并输出写入控制信号。

10. 发明授权

US08610656B2 Method for generating frame-start pulse signals inside source driver chip of LCD device 有权
标题翻译：用于在LCD器件的源极驱动器芯片内产生帧起始脉冲信号的方法
公开(公告)号：US08610656B2
公开(公告)日：2013-12-17
申请号：US12935164
申请日：2009-03-12
申请人： Man-Jeong Ko , An-Young Kim , Joon-Ho Na , Dae-Seong Kim
发明人： Man-Jeong Ko , An-Young Kim , Joon-Ho Na , Dae-Seong Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3611 , G09G2310/08 , G09G2330/06 , G09G2370/14
摘要： Provided is a method of driving a liquid crystal display apparatus, and more particularly, to a method of generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip of a liquid crystal display apparatus. Accordingly, by generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip unlike a conventional method where the frame start pulse signal is externally input, it is possible to reduce the number of input pins for inputting the frame start pulse signal and to remove an input line for inputting the frame start pulse signal in a process of mounting the source driver chip in a printed circuit board.
摘要翻译：提供一种驱动液晶显示装置的方法，更具体地说，涉及一种用于指示驱动液晶显示装置的源极驱动器芯片中的源极驱动器的特定功能的帧起始脉冲信号的方法。因此，通过产生用于指示驱动源驱动器芯片中的源极驱动器的特定功能的帧起始脉冲信号，与常规的外部输入帧起始脉冲信号的方法不同，可以减少输入引脚的数量在将源驱动器芯片安装在印刷电路板中的过程中，输入帧起始脉冲信号并去除用于输入帧起始脉冲信号的输入线。

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