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    • 5. 发明授权
      US06853225B2 Delay locked loop circuit with duty cycle correction function 有权
    • Delay locked loop circuit with duty cycle correction function
    • 具有占空比校正功能的延迟锁定环路电路
    • US06853225B2
    • 2005-02-08
    • US10315696
    • 2002-12-10
    • Seong Hoon Lee
    • Seong Hoon Lee
    • H03L7/00 , H03K5/00 , H03K5/13 , H03K5/151 , H03K5/156 , H03L7/07 , H03L7/081 , H03L7/06
    • H03L7/0812 , H03K5/133 , H03K5/151 , H03K5/1565 , H03K2005/00039 , H03L7/07
    • A delay locked loop (DLL) circuit having a structure in which a method of performing duty cycle correction (DCC) using two DLLs and an intermediate phase composer and a method of performing DCC by forming a closed loop using a negative feedback are combined with each other is provided. The DLL circuit includes a first DLL for receiving an external clock signal and generating a first clock signal and a second DLL for receiving an external clock signal and generating a second clock signal. The first clock signal and the second clock signal are synchronized with an external clock signal. The DLL circuit further includes an intermediate phase generation circuit for receiving the first and second clock signals and generating an intermediate phase clock signal and a DCC loop for receiving the intermediate phase clock signal and generating an output clock signal. The intermediate phase clock signal has an intermediate phase between the phases of the first and second clock signals. The output clock signal is generated through correction of the duty cycle of the intermediate phase clock signal using a value obtained by integrating the output clock signal.
    • 具有这样的结构的延迟锁定环（DLL）电路，其中使用两个DLL执行占空比校正（DCC）的方法和中间相位构成器以及通过使用负反馈形成闭环来执行DCC的方法与每个 其他提供。 DLL电路包括用于接收外部时钟信号并产生第一时钟信号的第一DLL和用于接收外部时钟信号并产生第二时钟信号的第二DLL。 第一时钟信号和第二时钟信号与外部时钟信号同步。 DLL电路还包括中间相位产生电路，用于接收第一和第二时钟信号并产生中间相位时钟信号和DCC回路，用于接收中间相位时钟信号并产生输出时钟信号。 中间相位时钟信号在第一和第二时钟信号的相位之间具有中间相位。 通过使用通过对输出时钟信号进行积分而获得的值来校正中间相位时钟信号的占空比来产生输出时钟信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US06680635B2 Apparatus and method for generating output clock signal having controlled timing 有权
    • Apparatus and method for generating output clock signal having controlled timing
    • 用于产生具有受控定时的输出时钟信号的装置和方法
    • US06680635B2
    • 2004-01-20
    • US10315370
    • 2002-12-10
    • Seong Hoon Lee
    • Seong Hoon Lee
    • H03L706
    • H03L7/0814 , H03L7/089
    • A delay locked loop circuit for improving the jitter index using a phase blender. The present delay locked loop circuit comprises a first delay circuit which receives an input clock signal in order to generate a first delayed input clock signal, and a second delay circuit which receives an input clock signal in order to generate a second delayed input clock signal. The first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delay circuit. The second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delay circuit. A phase blending circuit receives the first and second delayed input clock signals, blends the phases of the first and second delayed input clock signals, and generates a phase blended clock signal. In addition, a phase detection circuit is provided to receive a reference clock signal and the phase blended clock signal, generate a phase push signal PUSH in the case that the phase of the phase blended clock signal is ahead of that of the reference clock signal, and generate a phase pull signal PULL in the case that the phase of the phase blended clock signal is behind that of the reference clock signal.
    • 延迟锁定环电路，用于使用相位搅拌器改善抖动指数。 本延迟锁定环电路包括接收输入时钟信号以产生第一延迟输入时钟信号的第一延迟电路和接收输入时钟信号以产生第二延迟输入时钟信号的第二延迟电路。 第一延迟输入时钟信号是延迟由输入到第一延迟电路的第一延迟控制信号确定的周期的输入时钟信号。 第二延迟输入时钟信号是延迟输入到第二延迟电路的第二延迟控制信号确定的周期的输入时钟信号。 相位混合电路接收第一和第二延迟输入时钟信号，混合第一和第二延迟输入时钟信号的相位，并产生相位混合时钟信号。 此外，提供相位检测电路以接收参考时钟信号和相位混合时钟信号，在相位混合时钟信号的相位超前于参考时钟信号的相位的情况下产生相位推动信号PUSH， 并且在相位混合时钟信号的相位落后于参考时钟信号的相位的情况下产生相位拉信号PULL。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US08830769B2 Memory device and signal driving device thereof 有权
    • Memory device and signal driving device thereof
    • 存储器件及其信号驱动器件
    • US08830769B2
    • 2014-09-09
    • US13484541
    • 2012-05-31
    • Seong Hoon Lee
    • Seong Hoon Lee
    • G11C5/14
    • G11C7/062 , G11C7/1048 , G11C7/1069
    • A signal driving device includes a constant current circuit configured to provide a constant current, a first mirror circuit configured to generate a mirror current from the constant current and provide a voltage according to the mirror current of the constant current, a circuit comprising a switch device and configured to provide a driver current, a second mirror circuit configured to generate a mirror current of the driver current and output a voltage that includes a voltage drop caused when the mirror current of the driver current flows through a replica switch device, and a differential amplifier configured to receive the voltage from the first mirror circuit and the voltage from the second mirror circuit to provide a biased voltage for the bias circuit and thereby induce the driver current.
    • 信号驱动装置包括被配置为提供恒定电流的恒流电路，第一反射镜电路，被配置为根据恒定电流产生反射镜电流并根据恒定电流的反射镜电流提供电压;电路，包括开关装置 并且被配置为提供驱动器电流;第二镜电路，被配置为产生所述驱动器电流的反射镜电流，并输出包括当所述驱动器电流的反射镜电流流过复制开关器件时引起的电压降的电压;以及差分 放大器，被配置为接收来自第一镜像电路的电压和来自第二镜像电路的电压，以为偏置电路提供偏置电压，从而引起驱动器电流。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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