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1. 发明授权

US07768853B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07768853B2
公开(公告)日：2010-08-03
申请号：US12079995
申请日：2008-03-31
申请人： Hyo-Joo Ahn , Kyu-Chan Lee , Chul-Woo Yi
发明人： Hyo-Joo Ahn , Kyu-Chan Lee , Chul-Woo Yi
IPC分类号： G11C7/00
CPC分类号： G11C5/025 , G11C7/065 , G11C7/12 , G11C7/18 , G11C2207/002 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/11898
摘要： A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.
摘要翻译：半导体存储器件包括：具有设置在第一和第二衬底侧上的第一和第二存储单元阵列区域的衬底以及设置在第一和第二衬底侧的第一和第二存储单元阵列区域之间的第一和第二感测电路区域 ; 第一和第二位线耦合到第一存储单元阵列区域中的多个存储单元; 第一和第二互补位线耦合到第二存储单元阵列区域中的多个存储单元; 形成在第一感测电路区域中的第一和第二列选择晶体管，并且将第一位线和第一互补位线选择性地耦合到第一输入/输出（I / O）线和第一互补I / O线; 以及形成在第二感测电路区域中的第三和第四列选择晶体管，并且选择性地将第二位线和第二互补位线耦合到第二I / O线和第二互补I / O线。

2. 发明申请

US20080298111A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080298111A1
公开(公告)日：2008-12-04
申请号：US12079995
申请日：2008-03-31
申请人： Hyo-Joo Ahn , Kyu-Chan Lee , Chul-Woo Yi
发明人： Hyo-Joo Ahn , Kyu-Chan Lee , Chul-Woo Yi
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C5/025 , G11C7/065 , G11C7/12 , G11C7/18 , G11C2207/002 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/11898
摘要： A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.
摘要翻译：半导体存储器件包括：具有设置在第一和第二衬底侧上的第一和第二存储单元阵列区域的衬底以及设置在第一和第二衬底侧的第一和第二存储单元阵列区域之间的第一和第二感测电路区域 ; 第一和第二位线耦合到第一存储单元阵列区域中的多个存储单元; 第一和第二互补位线耦合到第二存储单元阵列区域中的多个存储单元; 形成在第一感测电路区域中的第一和第二列选择晶体管，并且将第一位线和第一互补位线选择性地耦合到第一输入/输出（I / O）线和第一互补I / O线; 以及形成在第二感测电路区域中的第三和第四列选择晶体管，并且选择性地将第二位线和第二互补位线耦合到第二I / O线和第二互补I / O线。

3. 发明授权

US07505353B2 Multi-port semiconductor memory device having variable access paths and method 有权
标题翻译：具有可变存取路径和方法的多端口半导体存储器件
公开(公告)号：US07505353B2
公开(公告)日：2009-03-17
申请号：US11466389
申请日：2006-08-22
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00 , G11C8/12 , G11C8/16 , G11C7/10
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供具有可变存取路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

4. 发明申请

US20100232249A1 MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR 有权
标题翻译：具有可变存取码的多端口半导体存储器件及其方法
公开(公告)号：US20100232249A1
公开(公告)日：2010-09-16
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

5. 发明授权

US07499364B2 Multi-port semiconductor memory device and signal input/output method therefor 有权
标题翻译：多端口半导体存储器件及其信号输入/输出方法
公开(公告)号：US07499364B2
公开(公告)日：2009-03-03
申请号：US11466415
申请日：2006-08-22
申请人： Hyo-Joo Ahn , Nam-Jong Kim
发明人： Hyo-Joo Ahn , Nam-Jong Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C8/16 , G11C29/1201 , G11C29/48
摘要： A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.
摘要翻译：因此，提供了多端口半导体存储器件和信号输入/输出方法。在一个实施例中，多端口半导体存储器件包括多个不同的输入/输出端口和存储器阵列。存储器阵列具有通过使用不同的输入/输出端口访问的至少一个存储器区域。不同的输入/输出端口包括输入/输出第一信号的第一输入/输出端口和与第一信号不同的第二信号被输入/输出的第二输入/输出端口。存储区域被分成多个存储区域。本发明提供减少测试针数量并提高测试效率的效果。

6. 发明授权

US08120986B2 Multi-port semiconductor memory device having variable access paths and method therefor 有权
标题翻译：具有可变存取路径的多端口半导体存储器件及其方法
公开(公告)号：US08120986B2
公开(公告)日：2012-02-21
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

7. 发明授权

US07596666B2 Multi-path accessible semiconductor memory device having port state signaling function 有权
标题翻译：具有端口状态信令功能的多路径可访问半导体存储器件
公开(公告)号：US07596666B2
公开(公告)日：2009-09-29
申请号：US11466399
申请日：2006-08-22
申请人： Hyo-Joo Ahn , Chi-Sung Oh
发明人： Hyo-Joo Ahn , Chi-Sung Oh
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1048 , G11C8/16 , G11C2207/105 , G11C2207/108
摘要： A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.
摘要翻译：提供了一种具有可由多个处理器随机访问的DRAM存储单元阵列中的共享存储区的多路径可访问半导体存储器件。多路径可访问半导体存储器件包括分配在存储单元阵列中的至少一个共享存储器区域，可操作地连接到对应于多个处理器的端口，由相应处理器使用的每个端口选择性地访问共享存储器区域。该设备还包括占用状态信令单元，用于向处理器输出端口占用状态信息，请求通过用于访问请求的端口访问共享存储区域，以指示是否允许对共享存储区域的访问。

8. 发明授权

US07586339B2 Output circuit and method thereof 有权
标题翻译：输出电路及其方法
公开(公告)号：US07586339B2
公开(公告)日：2009-09-08
申请号：US11430899
申请日：2006-05-10
申请人： Chi-Sung Oh , Hyo-Joo Ahn
发明人： Chi-Sung Oh , Hyo-Joo Ahn
IPC分类号： H03K17/04
CPC分类号： G11C7/1051 , G11C7/1057
摘要： An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.
摘要翻译：一种输出电路及其方法。在一个示例中，输出电路可以包括被配置为缓冲输出数据并将缓冲的输出数据传送到输出节点的输出缓冲器，输出缓冲器响应于触发信号初始化输出节点。在另一示例中，该方法可以包括响应于输出缓冲器使能信号来缓冲输出数据，将缓冲的输出数据传送到输出节点并响应于触发信号初始化输出缓冲器的输出节点。

9. 发明申请

US20070008787A1 Output circuit and method thereof 有权
标题翻译：输出电路及其方法
公开(公告)号：US20070008787A1
公开(公告)日：2007-01-11
申请号：US11430899
申请日：2006-05-10
申请人： Chi-Sung Oh , Hyo-Joo Ahn
发明人： Chi-Sung Oh , Hyo-Joo Ahn
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1057
摘要： An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.
摘要翻译：一种输出电路及其方法。在一个示例中，输出电路可以包括被配置为缓冲输出数据并将缓冲的输出数据传送到输出节点的输出缓冲器，输出缓冲器响应于触发信号初始化输出节点。在另一示例中，该方法可以包括响应于输出缓冲器使能信号来缓冲输出数据，将缓冲的输出数据传送到输出节点并响应于触发信号初始化输出缓冲器的输出节点。

10. 发明授权

US06813175B2 Interconnection layout of a semiconductor memory device 有权
标题翻译：半导体存储器件的互连布局
公开(公告)号：US06813175B2
公开(公告)日：2004-11-02
申请号：US10253926
申请日：2002-09-25
申请人： Hyo-Joo Ahn , Byong-Mo Moon , Hyun-Kyoung Kim
发明人： Hyo-Joo Ahn , Byong-Mo Moon , Hyun-Kyoung Kim
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage level when the data-write lines in a transitional state. Therefore, a coupling capacitance is not produced between adjacent data-write lines and adjacent data-read lines.
摘要翻译：互连布局包括交替布置的数据读取线和数据写入线。当数据读取线处于过渡状态时，数据写入线保持在接地电压电平，并且数据读取线保持在接地电压电平。因此，在相邻的数据写入线和相邻的数据读取线之间不产生耦合电容。

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