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1. 发明授权

US08373273B2 Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
标题翻译：形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法
公开(公告)号：US08373273B2
公开(公告)日：2013-02-12
申请号：US13533135
申请日：2012-06-26
申请人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
发明人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.
摘要翻译：形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。层间绝缘层的上表面被凹入以暴露电互连的侧壁。电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。该金属扩散阻挡层可以使用化学镀技术形成。

2. 发明申请

US20120267785A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY 有权
标题翻译：形成集成电路装置的方法，其具有金属扩散阻挡层和形成的器件的大分子互连
公开(公告)号：US20120267785A1
公开(公告)日：2012-10-25
申请号：US13533135
申请日：2012-06-26
申请人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
发明人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.
摘要翻译：形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。层间绝缘层的上表面被凹入以暴露电互连的侧壁。电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。该金属扩散阻挡层可以使用化学镀技术形成。

3. 发明授权

US08232200B1 Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
标题翻译：形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法
公开(公告)号：US08232200B1
公开(公告)日：2012-07-31
申请号：US13051732
申请日：2011-03-18
申请人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
发明人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.
摘要翻译：形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。层间绝缘层的上表面被凹入以暴露电互连的侧壁。电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。该金属扩散阻挡层可以使用化学镀技术形成。

4. 发明申请

US20060102941A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20060102941A1
公开(公告)日：2006-05-18
申请号：US10986060
申请日：2004-11-12
申请人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
发明人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , G11C11/22 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.
摘要翻译：公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜，以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

5. 发明申请

US20050239219A1 Process for fabrication of a ferrocapacitor with a large effective area 审中-公开
标题翻译：具有大面积有效面积的铁电体的制造方法
公开(公告)号：US20050239219A1
公开(公告)日：2005-10-27
申请号：US10831957
申请日：2004-04-26
申请人： Bum-Ki Moon
发明人： Bum-Ki Moon
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8242 , H01L29/76
CPC分类号： H01L28/84 , H01L27/10852 , H01L28/55 , H01L28/90
摘要： In a ferroelectic capacitor including a dielectric ferroelectric element sandwiched between a bottom electrode and top electrode, the bottom electrode is formed with a ridged structure, and the ferroelectric layer is formed over it and on its sides. Thus the dielectric between the top and bottom electrodes includes not just horizontal sections but also non-horizontal sections. The inventive structure thus has a higher effective capacitor area compared to the overall area of the device. This has two advantages. Firstly, it means that the total charge which can be stored in the device is higher. Secondly, it means that damage to the electrodes and the ferroelectric element at their edges regions occupies a lower proportion of the effective area of the device. The ridged structure of the bottom electrode may be due to it being formed over a ridged substructure, or because it is itself selectively etched.
摘要翻译：在包含夹在底部电极和顶部电极之间的介质铁电元件的铁电电容器中，底部电极形成为脊状结构，并且铁电层形成在其上并在其侧面。因此，顶部和底部电极之间的电介质不仅包括水平部分，而且包括非水平部分。因此，与本装置的总体面积相比，本发明的结构具有更高的有效电容器面积。这有两个优点。首先，这意味着可以存储在设备中的总电荷较高。其次，这意味着电极和铁电元件在其边缘区域的损坏占设备有效面积的较低比例。底部电极的脊状结构可能是由于其形成在隆起的子结构之上，或者由于其本身被选择性地蚀刻。

6. 发明授权

US07042037B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07042037B1
公开(公告)日：2006-05-09
申请号：US10986060
申请日：2004-11-12
申请人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
发明人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
IPC分类号： H01L31/062
CPC分类号： H01L28/55 , G11C11/22 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.
摘要翻译：公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜，以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

7. 发明授权

US07119021B2 Ferroelectric capacitor devices and a method for compensating for damage to a capacitor caused by etching 有权
标题翻译：铁电电容器装置和用于补偿由蚀刻引起的电容器损坏的方法
公开(公告)号：US07119021B2
公开(公告)日：2006-10-10
申请号：US10703870
申请日：2003-11-07
申请人： Bum-Ki Moon
发明人： Bum-Ki Moon
IPC分类号： H01L21/302
CPC分类号： H01L28/56 , H01L28/75
摘要： A ferroelectric capacitor in which damage caused by etching exposed faces of a ferroelectric layer of the capacitor is compensated by depositing a seeding layer of ferroelectric material such as PZT on one or more exposed faces of the ferroelectric layer and depositing an electrode layer made of conductive material such as platinum on the seeding layer. An oxygen annealing recovery process is applied to the device. The seeding layer can transform the phase of the damaged surfaces from amorphous to crystalline during the recovery annealing process and, at the same time, provide the damaged surfaces of the ferroelectric layer with missing element(s), for example lead. The oxygen necessary for recovery of the damage may be obtained through the platinum layer from the oxygen atmosphere.
摘要翻译：通过在铁电层的一个或多个暴露面上沉积诸如PZT的铁电材料的接种层来补偿由腐蚀电容器的铁电层的暴露面引起的损伤的铁电电容器，并且沉积由导电材料制成的电极层如接种层上的铂。将氧退火恢复过程应用于该装置。接种层可以在恢复退火过程中将受损表面的相位从无定形转变为结晶，并且同时提供具有缺失元件（例如铅）的铁电层的受损表面。可以通过来自氧气氛的铂层获得回收损伤所必需的氧。

8. 发明授权

US07071506B2 Device for inhibiting hydrogen damage in ferroelectric capacitor devices 失效
标题翻译：用于抑制铁电电容器件中的氢损伤的装置
公开(公告)号：US07071506B2
公开(公告)日：2006-07-04
申请号：US10655757
申请日：2003-09-05
申请人： Bum-Ki Moon , Karl Hornik , Haoren Zhuang , Ulrich Egger , Jenny Lian , Andreas Hilliger
发明人： Bum-Ki Moon , Karl Hornik , Haoren Zhuang , Ulrich Egger , Jenny Lian , Andreas Hilliger
IPC分类号： H01L29/76
CPC分类号： H01L28/57 , H01L27/0805 , H01L27/11507
摘要： A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.
摘要翻译：铁电电容器装置包括基板，穿过基板的接触插塞，形成在基板上的第一电极，第一电极电连接到所述插头，形成在第一电极上的铁电层，形成在铁电体上的第二电极层，在第二电极上的一个或多个第一封装层，在器件上延伸的封装层以及封装层上的一个或多个储氢材料层。一个或多个第二封装层可以形成在一个或多个储氢材料层上。

9. 发明申请

US20060003469A1 Process for fabrication of a ferrocapacitor 有权
标题翻译：制造铁电体的方法
公开(公告)号：US20060003469A1
公开(公告)日：2006-01-05
申请号：US10881338
申请日：2004-06-30
申请人： Karl Hornik , Rainer Bruchhaus , Bum-Ki Moon
发明人： Karl Hornik , Rainer Bruchhaus , Bum-Ki Moon
IPC分类号： H01L21/00
CPC分类号： H01L21/02197 , H01L21/02304 , H01L28/56
摘要： In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the Al2O3 into a TEOS structure beneath.
摘要翻译：在制造包括在Al 2 O 3层上提供铁电PZT元件的铁电体的方法中，Al 2 O 3 3 / SUB层用包含PZT和TiO 2层的种子层覆盖。然后在种子层上形成较厚的PZT层并结晶。通过该方法，厚PZT层的结晶度大大提高，其取向提高到（111）方向。此外，种子层减少了从厚PZT层（例如通过Al 2 O 3 3）到下面的TEOS结构的Pb的向下衍射。

10. 发明授权

US07169658B2 Method for formation of an ultra-thin film and semiconductor device containing such a film 有权
标题翻译：用于形成超薄膜的方法和包含这种膜的半导体器件
公开(公告)号：US07169658B2
公开(公告)日：2007-01-30
申请号：US10767928
申请日：2004-01-29
申请人： Bum-Ki Moon
发明人： Bum-Ki Moon
IPC分类号： H01L21/336
CPC分类号： H01L21/02197 , H01L21/02186 , H01L21/022 , H01L21/02318 , H01L21/28194 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L29/517
摘要： A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.
摘要翻译：制造超薄PZT烧绿石膜的方法包括提供包括基底层的结构，并且在基底层上形成相互接触的钛层和PZT层。将该结构退火以在所述基底层上形成PZT烧绿石层。因此可以制造具有超薄PZT层的新型器件。

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