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1. 发明专利

JP2013140665A Gate driving circuit and shift registers 审中-公开
标题翻译：门驱动电路和移位寄存器
公开(公告)号：JP2013140665A
公开(公告)日：2013-07-18
申请号：JP2012287903
申请日：2012-12-28
申请人： Hydis Technologies Co Ltd , ヒディステクノロジーズカンパニー,リミテッドHydis Technologies Co.,Ltd.
发明人： SON KI MIN , AN JOON SUNG , LEE WON-HEE
IPC分类号： G11C19/28 , G09G3/20 , G11C19/00 , H04N5/66
CPC分类号： G09G5/00 , G09G3/3677 , G09G2310/0286 , G09G2310/0291 , G11C19/28 , G11C19/287
摘要： PROBLEM TO BE SOLVED: To provide: a gate driving circuit including shift registers to respectively supply scan signals to a plurality of gate lines; and the shift registers.SOLUTION: Each shift register comprises: an input unit which outputs a directional input signal to a first node; an inverter unit which generates an inverting signal to a signal at the first node, and outputs it to a second node; and an output unit which includes a pull-up unit activating an output clock signal on the basis of the signal at the first node and outputting an output signal, and a pull-down unit activating and outputting a pull-down output signal on the basis of a signal at the second node. The input unit realizes bidirectional driving by changing signal connection states, and the inverter unit carries out perfect inverting by coupling with a control clock signal.
摘要翻译：要解决的问题：提供：包括移位寄存器的栅极驱动电路，以分别向多条栅极线提供扫描信号; 和移位寄存器。解决方案：每个移位寄存器包括：向第一节点输出定向输入信号的输入单元; 反相器单元，其产生与第一节点处的信号的反相信号，并将其输出到第二节点; 以及输出单元，其包括上拉单元，其基于第一节点处的信号来激活输出时钟信号并输出输出信号;以及下拉单元，在该基础上激活并输出下拉输出信号在第二节点处的信号。输入单元通过改变信号连接状态实现双向驱动，逆变器单元通过与控制时钟信号耦合来实现完美的反相。

2. 发明专利

JP2013069400A Shift register and gate drive circuit using the same 有权
标题翻译：移位寄存器和门驱动电路
公开(公告)号：JP2013069400A
公开(公告)日：2013-04-18
申请号：JP2012198066
申请日：2012-09-10
申请人： Hydis Technologies Co Ltd , ハイディステクノロジーズカンパニーリミテッドHydis Technologies Co., Ltd.
发明人： SON KI MIN
IPC分类号： G11C19/28 , G09G3/20 , G11C19/00
CPC分类号： G09G3/2085 , G09G3/20 , G09G2310/0283 , G09G2310/0286
摘要： PROBLEM TO BE SOLVED: To improve operational reliability while reducing components as compared with an existing structure.SOLUTION: Each of a plurality of shift registers includes: an input section for outputting a direction input signal to a first node by an output signal from the shift register at a preceding or following stage of the shift register; an inverter section which is controlled by a second clock signal, is connected to the first node, generates an inverted signal with respect to a signal of the first node and outputs the inverted signal to a second node; an output section including a pull-up section which is connected to the first node, synchronizes with a first clock signal, activates the first clock signal by the signal of the first node and outputs an output signal to a gate line and a pull-down section which activates a pull-down output signal by a signal of the second node and outputs an output signal to the gate line; and a reset section for periodically resetting the first node by the second clock signal.
摘要翻译：要解决的问题：与现有结构相比，提高运行可靠性，同时减少组件。多个移位寄存器中的每一个包括：输入部分，用于在移位寄存器的前一个或后一个阶段通过来自移位寄存器的输出信号将方向输入信号输出到第一节点; 由第二时钟信号控制的逆变器部分连接到第一节点，相对于第一节点的信号产生反相信号，并将反相信号输出到第二节点; 输出部分，包括连接到第一节点的上拉部分，与第一时钟信号同步，通过第一节点的信号激活第一时钟信号，并将输出信号输出到门线和下拉该部分通过第二节点的信号激活下拉输出信号，并将输出信号输出到栅极线; 以及用于通过第二时钟信号周期性地重置第一节点的复位部分。版权所有（C）2013，JPO＆INPIT

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