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1. 发明授权

US06499046B1 Saturation detection apparatus and method therefor 有权
标题翻译：饱和度检测装置及其方法
公开(公告)号：US06499046B1
公开(公告)日：2002-12-24
申请号：US09315545
申请日：1999-05-20
申请人： Huy Van Nguyen , Charles Philip Roth
发明人： Huy Van Nguyen , Charles Philip Roth
IPC分类号： G06F738
CPC分类号： G06F7/49921 , G06F9/30014 , G06F9/30036
摘要： An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input operands, and a plurality of saturation value signals. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.
摘要翻译：实现了用于饱和检测的装置及其方法。选择电路选择用于在接收一对输入操作数的加法器的输出和多个饱和值信号之间输出的数据值信号。每个输入操作数可以包括预选数据类型的多个子向量操作数，每个数据类型具有相应的长度。选择电路响应多个第二信号选择数据值信号。第二信号是从子载波操作数的进位信号和使用执行指令的指令信息产生的第一信号产生的。第二信号可以通过逻辑地组合第一信号与进位传播来产生，从接收子载波操作数作为输入的进位先行逻辑进行产生和执行信号。

2. 发明授权

US06519620B1 Saturation select apparatus and method therefor 有权
标题翻译：饱和选择装置及其方法
公开(公告)号：US06519620B1
公开(公告)日：2003-02-11
申请号：US09296877
申请日：1999-04-22
申请人： Huy Van Nguyen , Michael Putrino , Charles Philip Roth
发明人： Huy Van Nguyen , Michael Putrino , Charles Philip Roth
IPC分类号： G06F738
CPC分类号： G06F7/49921 , G06F7/50
摘要： A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.
摘要翻译：实现饱和选择装置和方法。提供加法器中的后级逻辑块，其将饱和选择控制信号与和产生信号组合。响应于无符号饱和指令来确定第一饱和选择控制，并且响应于带符号饱和指令断言第二饱和选择控制。如果选择控制被确认，则每个逻辑块输出相应饱和值的相应位。响应于模数模式指令，两个选择控制信号被否定，并且每个逻辑块输出由该指令实现的算术运算（和或差）的相应位。

3. 发明授权

US06470440B1 Vector compare and maximum/minimum generation apparatus and method therefor 失效
标题翻译：矢量比较和最大/最小生成装置及其方法
公开(公告)号：US06470440B1
公开(公告)日：2002-10-22
申请号：US09315546
申请日：1999-05-20
申请人： Huy Van Nguyen , Charles Philip Roth
发明人： Huy Van Nguyen , Charles Philip Roth
IPC分类号： G06F9305
CPC分类号： G06F9/30021 , G06F9/30036
摘要： An apparatus for compare and maximum/minimum and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an a pair of vector operands and “true” and “false” comparison value signals for the corresponding operand data type. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.
摘要翻译：实现了比较和最大/最小的装置及其方法。选择电路选择用于在一对矢量操作数之间输出的数据值信号，以及对应的操作数数据类型的“真”和“假”比较值信号。每个输入操作数可以包括预选数据类型的多个子向量操作数，每个数据类型具有相应的长度。选择电路响应多个第二信号选择数据值信号。第二信号是从子载波操作数的进位信号和使用执行指令的指令信息产生的第一信号产生的。第二信号可以通过逻辑地组合第一信号与进位传播来产生，从接收子载波操作数作为输入的进位先行逻辑进行产生和执行信号。

4. 发明授权

US06308189B1 Apparatus for partial logical shifts and method therefor 失效
标题翻译：用于部分逻辑移位的装置及其方法
公开(公告)号：US06308189B1
公开(公告)日：2001-10-23
申请号：US09089716
申请日：1998-06-03
申请人： Huy Van Nguyen
发明人： Huy Van Nguyen
IPC分类号： G06F700
CPC分类号： G06F5/015
摘要： An apparatus and method for performing partial logical shifts of a multiple-word logical signal is implemented. Portions of an input logical signal to be shifted are input to a plurality of barrel shifters. Each barrel shifter performs a rotation of its associated input portion. Each corresponding rotated portion output therefrom is masked with a preselected mask having m trailing zero bits, for a left shift, or m leading zero bits, for a right shift. Rotated portions from barrel shifters succeeding, for a left shift, or preceding, for a right shift, the barrel shifter associated with the corresponding rotated portion are masked with a complementary mask and logically combined with the masked rotated portion from the corresponding barrel shifter to form a corresponding portion of the shifted output signal.
摘要翻译：实施用于执行多字逻辑信号的部分逻辑移位的装置和方法。要移位的输入逻辑信号的部分被输入到多个桶形移位器。每个桶形移位器执行其相关联的输入部分的旋转。对于右移，对于左移或m前导零位，用对于其输出的每个对应的旋转部分被掩蔽，具有m个尾随零位的预选掩模。来自桶形移位器的旋转部分，对于左移或左前移动，对于右移，与相应的旋转部分相关联的桶形移位器用互补掩模掩蔽，并与来自相应桶形移位器的被屏蔽的旋转部分逻辑组合，以形成移位输出信号的相应部分。

5. 发明申请

US20080194557A1 Methods and compositions for the treatment of pain, inflammation and cancer 审中-公开
标题翻译：用于治疗疼痛，炎症和癌症的方法和组合物
公开(公告)号：US20080194557A1
公开(公告)日：2008-08-14
申请号：US12015714
申请日：2008-01-17
申请人： Joseph Barbosa , Simon D.P. Baugh , Qiang Han , Victoria K. Lombardo , Huy Van Nguyen , Praveen K. Pabba , Kristen M. Terranova
发明人： Joseph Barbosa , Simon D.P. Baugh , Qiang Han , Victoria K. Lombardo , Huy Van Nguyen , Praveen K. Pabba , Kristen M. Terranova
IPC分类号： A61K31/5377 , C07D217/22 , A61K31/47 , C07D487/04 , A61P29/00 , C07D231/56 , A61K31/519 , C07D413/02
CPC分类号： C07C211/59 , C07C211/44 , C07C211/60 , C07C237/40 , C07C255/52 , C07C275/30 , C07D209/08 , C07D213/74 , C07D215/38 , C07D215/44 , C07D215/60 , C07D217/06 , C07D217/22 , C07D231/56 , C07D233/64 , C07D237/28 , C07D237/34 , C07D239/94 , C07D261/20 , C07D275/04 , C07D277/82 , C07D295/135 , C07D307/85 , C07D311/08 , C07D311/68 , C07D333/20 , C07D333/66 , C07D401/04 , C07D401/06 , C07D401/10 , C07D403/04 , C07D403/06 , C07D405/04 , C07D405/06 , C07D405/12 , C07D409/04 , C07D409/12 , C07D413/04 , C07D413/06 , C07D417/06 , C07D417/14 , C07D471/04 , C07D473/34 , C07D487/04 , C07D491/04 , C07D495/04 , C07D498/04
摘要： This invention relates to methods of treating, managing and preventing pain, inflammation, cancer, and ocular diseases and disorders, and to compounds and pharmaceutical compositions useful in such methods.
摘要翻译：本发明涉及治疗，控制和预防疼痛，炎症，癌症和眼部疾病和病症的方法，以及可用于这些方法的化合物和药物组合物。

6. 发明授权

US06401108B1 Floating point compare apparatus and methods therefor 失效
标题翻译：浮点比较装置及其方法
公开(公告)号：US06401108B1
公开(公告)日：2002-06-04
申请号：US09282612
申请日：1999-03-31
申请人： Huy Van Nguyen
发明人： Huy Van Nguyen
IPC分类号： G06F702
CPC分类号： G06F7/026 , G06F7/483
摘要： Floating-point compare apparatus and methods are implemented. An adder generates a difference in moduli of first and second input operands. A sign bit of the second input operand provides a carry-in bit to an adder. In a first embodiment, the first and second input operands correspond to first and second source operands of the executing floating-point compare instruction. Comparison logic generates the compare result in response to a sign bit of the difference, sign bits of the first and second input operands, and a signal that is asserted if the operands are equal, and if the floating-point compare instruction being executed is A≧B, and negated otherwise. In a second embodiment, the first and second input operands are derived from the first and second source operands via switching logic that interchanges the operands in response to predecoded instruction information. The operands are interchanged, whereby the first and second input operands correspond, respectively, to the second and first source operands if the floating-point compare instruction being executed is A≧B.
摘要翻译：实现了浮点比较装置和方法。加法器产生第一和第二输入操作数的模数差。第二个输入操作数的符号位向加法器提供进位位。在第一实施例中，第一和第二输入操作数对应于执行浮点比较指令的第一和第二源操作数。比较逻辑响应于差异的符号位产生比较结果，第一和第二输入操作数的符号位，以及如果操作数相等则被断言的信号，并且如果正在执行的浮点比较指令是A > = B，否则否定。在第二实施例中，第一和第二输入操作数通过交换逻辑从第一和第二源操作数导出，该逻辑根据预解码的指令信息交换操作数。操作数互换，如果正在执行的浮点比较指令是A> = B，则第一和第二输入操作数分别对应于第二和第一源操作数。

7. 发明申请

US20080200458A1 Methods and compositions for the treatment of body composition disorders 审中-公开
标题翻译：用于治疗身体组成障碍的方法和组合物
公开(公告)号：US20080200458A1
公开(公告)日：2008-08-21
申请号：US12015728
申请日：2008-01-17
申请人： Joseph Barbosa , Simon D.P. Baugh , Qiang Han , Victoria K. Lombardo , Huy Van Nguyen , Praveen K. Pabba , Kristen M. Terranova
发明人： Joseph Barbosa , Simon D.P. Baugh , Qiang Han , Victoria K. Lombardo , Huy Van Nguyen , Praveen K. Pabba , Kristen M. Terranova
IPC分类号： A61K31/5377 , C12N9/99 , A61K31/47 , A61K31/519 , A61K31/437 , A61K31/502 , A61P3/00 , A61K31/4365 , A61K31/404 , A61K31/136 , A61K31/4164 , A61K31/343
CPC分类号： C07D231/56 , C07C211/52 , C07C211/58 , C07C211/59 , C07C211/60 , C07C211/61 , C07C215/44 , C07C217/08 , C07C217/54 , C07C217/58 , C07C217/92 , C07C225/22 , C07C229/16 , C07C237/40 , C07C237/44 , C07C237/48 , C07C255/58 , C07C275/30 , C07C2602/08 , C07C2602/10 , C07C2603/10
摘要： This invention relates to methods of treating, managing and preventing body composition disorders, and to compounds and pharmaceutical compositions useful in such methods.
摘要翻译：本发明涉及治疗，控制和预防身体组成障碍的方法，以及可用于这些方法的化合物和药物组合物。

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