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1. 发明授权

US06600338B1 Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage 有权
标题翻译：输入接收电路从高外部电压到低内部电源电压的装置和方法
公开(公告)号：US06600338B1
公开(公告)日：2003-07-29
申请号：US09849755
申请日：2001-05-04
申请人： Huy Nguyen , Roxanne Vu , Benedict Lau , Jade Kizer
发明人： Huy Nguyen , Roxanne Vu , Benedict Lau , Jade Kizer
IPC分类号： H03K190175
CPC分类号： H03K19/018528
摘要： A circuit and method for level-shifting an input signal are disclosed that provide for level-shifting of a the input signal where an external voltage level is greater than an internal voltage of the signal. In the present invention, the input signal is compared to a reference signal to produce a differential current signal reflecting the logic level of the input signal. The differential current signal is reflected through a pair of current mirrors operating from the external voltage level to drive a pair of resistive loads. Each of the resistive loads is coupled in series with a current sink between the internal supply voltage and a ground voltage. As a result, the input signal may be received and level-shifted with gain even when the internal supply voltage is less than twice a transistor threshold voltage without introducing significant distortion to the received signal.
摘要翻译：公开了用于电平移位输入信号的电路和方法，其提供输入信号的电平移位，其中外部电压电平大于信号的内部电压。在本发明中，将输入信号与参考信号进行比较，以产生反映输入信号的逻辑电平的差分电流信号。差分电流信号通过从外部电压电平工作的一对电流镜反射，以驱动一对电阻负载。每个电阻负载与内部电源电压和接地电压之间的电流吸收器串联耦合。结果，即使当内部电源电压小于晶体管阈值电压的两倍时，也可以接收输入信号并进行电平移位，而不会对接收到的信号引入显着的失真。

2. 发明授权

US06798243B1 Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage 有权
标题翻译：输入接收电路从高外部电压到低内部电源电压的装置和方法
公开(公告)号：US06798243B1
公开(公告)日：2004-09-28
申请号：US10629167
申请日：2003-07-28
申请人： Huy Nguyen , Roxanne Vu , Benedict Lau , Jade Kizer
发明人： Huy Nguyen , Roxanne Vu , Benedict Lau , Jade Kizer
IPC分类号： H03K190175
CPC分类号： H03K19/018528
摘要： A circuit and method for level-shifting an input signal are disclosed that provide for level-shifting of a the input signal where an external voltage level is greater than an internal voltage of the signal. In the present invention, the input signal is compared to a reference signal to produce a differential current signal reflecting the logic level of the input signal. The differential current signal is reflected through a pair of current mirrors operating from the external voltage level to drive a pair of resistive loads. Each of the resistive loads is coupled in series with a current sink between the internal supply voltage and a ground voltage. As a result, the input signal may be received and level-shifted with gain even when the internal supply voltage is less than twice a transistor threshold voltage without introducing significant distortion to the received signal.
摘要翻译：公开了用于电平移位输入信号的电路和方法，其提供输入信号的电平移位，其中外部电压电平大于信号的内部电压。在本发明中，将输入信号与参考信号进行比较，以产生反映输入信号的逻辑电平的差分电流信号。差分电流信号通过从外部电压电平工作的一对电流镜反射，以驱动一对电阻负载。每个电阻负载与内部电源电压和接地电压之间的电流吸收器串联耦合。结果，即使当内部电源电压小于晶体管阈值电压的两倍时，也可以接收输入信号并进行电平移位，而不会对接收到的信号引入显着的失真。

3. 发明申请

US20050030071A1 PHASE SYNCHRONIZATION FOR WIDE AREA INTEGRATED CIRCUITS 有权
标题翻译：宽区域集成电路的相位同步
公开(公告)号：US20050030071A1
公开(公告)日：2005-02-10
申请号：US10633831
申请日：2003-08-04
申请人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
发明人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
IPC分类号： G06F1/10 , H03L7/00 , H03L7/06
CPC分类号： G06F1/10 , G06F1/12 , H03L7/00
摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
摘要翻译：用于同步计时器件的电路和方法，例如寄存器。由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

4. 发明申请

US20050046454A1 Phase synchronization for wide area integrated circuits 有权
标题翻译：广域集成电路的相位同步
公开(公告)号：US20050046454A1
公开(公告)日：2005-03-03
申请号：US10963698
申请日：2004-10-13
申请人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
发明人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
IPC分类号： G06F1/10 , H03L7/00 , H03L7/06
CPC分类号： G06F1/10 , G06F1/12 , H03L7/00
摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
摘要翻译：用于同步计时器件的电路和方法，例如寄存器。由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

5. 发明申请

US20070124636A1 PHASE SYNCHRONIZATION FOR WIDE AREA INTEGRATED CIRCUITS 有权
标题翻译：宽区域集成电路的相位同步
公开(公告)号：US20070124636A1
公开(公告)日：2007-05-31
申请号：US11620309
申请日：2007-01-05
申请人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
发明人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
IPC分类号： G01R31/28
CPC分类号： G06F1/10 , G06F1/12 , H03L7/00
摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
摘要翻译：用于同步计时器件的电路和方法，例如寄存器。由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

6. 发明授权

US07095265B2 PVT-compensated clock distribution 有权
标题翻译： PVT补偿时钟分配
公开(公告)号：US07095265B2
公开(公告)日：2006-08-22
申请号：US11101958
申请日：2005-04-08
申请人： Huy Nguyen , Roxanne Vu , Benedict Lau
发明人： Huy Nguyen , Roxanne Vu , Benedict Lau
IPC分类号： G06F1/04
CPC分类号： H03K5/133 , G06F1/10 , H03K2005/00039 , H03K2005/00078 , H03K2005/00143
摘要： Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.
摘要翻译：描述了用于分配低偏移，可预测的定时时钟信号的方法和系统。时钟分配网络包括多个可动态调整的时钟缓冲器。连接到每个时钟缓冲器的控制电路响应于过程，电压和温度变化来控制通过时钟缓冲器的延迟，并且因此通过网络维持相对恒定的信号传播延迟。在一个实施例中，每个时钟缓冲器包括倾斜偏移电路，其增加或减去由PVT控制电路提供的PVT补偿延迟值，以简化时钟偏差最小化。

7. 发明申请

US20050237117A1 PLL and method for providing a single/multiple adjustable frequency range 有权
标题翻译： PLL和提供单/多个可调频率范围的方法
公开(公告)号：US20050237117A1
公开(公告)日：2005-10-27
申请号：US10828667
申请日：2004-04-21
申请人： Roxanne Vu , Huy Nguyen , Benedict Lau
发明人： Roxanne Vu , Huy Nguyen , Benedict Lau
IPC分类号： H03L7/00 , H03L7/089 , H03L7/093 , H03L7/107 , H03L7/18 , H04L7/033
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/107 , H03L7/1072 , H03L7/1075 , H03L7/18 , H04L7/033
摘要： A PLL circuit and method provides an adjustable operating frequency range by using at least two VCOs. In an embodiment of the present invention, circuit components of a PLL are adjusted in order to obtain a selected frequency range. In particular, a gain of a charge pump and resistance of a filter is adjusted responsive to a control signal. In alternate embodiments of the present invention, a voltage regulator, including an operational amplifier, is coupled to the output of the filter and the respective inputs of two VCOs. An output multiplexer then selects a VCO output responsive to the control signal. In another embodiment of the present invention, a multiplexer is coupled to the output of the voltage regulator to select which VCO receives a buffered voltage. In another embodiment of the present invention, respective operational amplifiers that may be enabled or disabled responsive to the control signal are coupled to a filter output and respective VCO inputs in order to provide an adjustable frequency range.
摘要翻译： PLL电路和方法通过使用至少两个VCO提供可调节的工作频率范围。在本发明的一个实施例中，调整PLL的电路部件以获得选定的频率范围。特别地，响应于控制信号调整电荷泵的增益和滤波器的电阻。在本发明的替代实施例中，包括运算放大器的电压调节器耦合到滤波器的输出端和两个VCO的相应输入端。然后，输出多路复用器响应于控制信号选择VCO输出。在本发明的另一个实施例中，多路复用器耦合到电压调节器的输出以选择哪个VCO接收缓冲电压。在本发明的另一个实施例中，可以响应于控制信号使能或禁用的各个运算放大器被耦合到滤波器输出和相应的VCO输入，以便提供可调节的频率范围。

8. 发明申请

US20050226088A1 Method and apparatus for low capacitance, high output impedance driver 有权
标题翻译：低电容，高输出阻抗驱动器的方法和装置
公开(公告)号：US20050226088A1
公开(公告)日：2005-10-13
申请号：US11142574
申请日：2005-06-01
申请人： Leung Yu , Roxanne Vu , Benedict Lau , Huy Nguyen , James Gasbarro
发明人： Leung Yu , Roxanne Vu , Benedict Lau , Huy Nguyen , James Gasbarro
IPC分类号： G11C7/10 , G11C8/00 , G11C29/02 , H03K19/003
CPC分类号： G11C7/1057 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2029/0401 , G11C2029/5004 , G11C2207/2254 , H03K19/00384
摘要： An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.
摘要翻译：描述了具有反馈回路的装置。当数据线电压接近参考电压时，反馈回路具有接近稳态的输出。该装置还包括驱动数据线的驱动晶体管。驱动晶体管具有由反馈环路输出控制的输出阻抗，当反馈环路输出达到稳定状态时，反馈环路输出将驱动晶体管输出阻抗保持在高输出阻抗区域内。

9. 发明申请

US20050057278A1 Push-pull output driver 失效
标题翻译：推挽输出驱动
公开(公告)号：US20050057278A1
公开(公告)日：2005-03-17
申请号：US10925544
申请日：2004-08-24
申请人： Huy Nguyen , Benedict Lau , Roxanne Vu
发明人： Huy Nguyen , Benedict Lau , Roxanne Vu
IPC分类号： H03K17/16 , H03K19/00 , H03K19/017 , H03K19/094
CPC分类号： H03K19/0013 , H03K17/166 , H03K19/01735
摘要： An improved, open-loop push-pull driver is described. Closed-loop feedback loop techniques for control of the push-pull driver are described. These techniques are particularly well adapted to control shoot-through current in a push-pull driver circuit.
摘要翻译：描述了改进的开环推挽式驱动器。描述了用于控制推挽驱动器的闭环反馈回路技术。这些技术特别适用于控制推挽式驱动电路中的直通电流。

10. 发明授权

US07307461B2 System and method for adaptive duty cycle optimization 失效
标题翻译：自适应占空比优化的系统和方法
公开(公告)号：US07307461B2
公开(公告)日：2007-12-11
申请号：US10661225
申请日：2003-09-12
申请人： Huy Nguyen , Roxanne Vu , Leung Yu , Benedict Lau
发明人： Huy Nguyen , Roxanne Vu , Leung Yu , Benedict Lau
IPC分类号： H03K7/08
CPC分类号： G11C7/1093 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.
摘要翻译：一种用于配置接收机的系统和方法，使得接收机时钟的占空比与接收到的数据信号的占空比精确匹配。该自适应系统和方法校准接收机的占空比，以优化不同数据信号类型和不同从设备的接收机定时裕度。在一个实施例中，占空比校正电路将接收器时钟与预定的占空比相匹配。然后，接收机时钟被配置为具有基于接收的特定数据信号从预定占空比偏移的占空比。在利用时钟树的接收机系统中，时钟树的各个分支被配置成使各自的占空比歪斜以匹配从特定发送设备接收的数据信号的占空比。

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