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1. 发明申请

US20080225611A1 METHOD AND APPARATUS FOR IMPROVING SRAM CELL STABILTY BY USING BOOSTED WORD LINES 有权
标题翻译：通过使用增强字线改善SRAM单元稳定性的方法和装置
公开(公告)号：US20080225611A1
公开(公告)日：2008-09-18
申请号：US12130472
申请日：2008-05-30
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

2. 发明授权

US07934181B2 Method and apparatus for improving SRAM cell stability by using boosted word lines 有权
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US07934181B2
公开(公告)日：2011-04-26
申请号：US12130472
申请日：2008-05-30
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G06F17/50 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

3. 发明授权

US07579655B2 Transistor structure having interconnect to side of diffusion and related method 失效
标题翻译：具有与扩散侧相互连接的晶体管结构及相关方法
公开(公告)号：US07579655B2
公开(公告)日：2009-08-25
申请号：US11275475
申请日：2006-01-09
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823871 , H01L29/665 , H01L29/66636 , H01L29/66772
摘要： A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical contact with the interconnect. The low-resistivity local interconnect is advantageous for use with stressed liner films since a conductor can contact the interconnect at a distance from the diffusion, thus allowing electrical contact without having to interrupt the stress liner film where it is most effective. Several embodiments of methods of electrically connecting a diffusion to an interconnect are also disclosed.
摘要翻译：公开了一种晶体管结构，其包括至少一个晶体管，其包括扩散和电连接到扩散侧的互连和与互连电接触的导体。低电阻率局部互连有利于与应力衬垫膜一起使用，因为导体可以在距离扩散一定距离处接触互连，从而允许电接触，而不必中断其中最有效的应力衬垫膜。还公开了将扩散电连接到互连的方法的几个实施例。

4. 发明授权

US07512908B2 Method and apparatus for improving SRAM cell stability by using boosted word lines 失效
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US07512908B2
公开(公告)日：2009-03-31
申请号：US11450610
申请日：2006-06-09
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G06F17/50 , G06F9/45 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

5. 发明申请

US20070291528A1 Method and apparatus for improving SRAM cell stability by using boosted word lines 失效
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US20070291528A1
公开(公告)日：2007-12-20
申请号：US11450610
申请日：2006-06-09
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

6. 发明授权

US08835261B2 Field effect transistor structure and method of forming same 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US08835261B2
公开(公告)日：2014-09-16
申请号：US13046902
申请日：2011-03-14
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L21/31
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
摘要翻译：本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

7. 发明授权

US08417503B2 System and method for target-based compact modeling 失效
公开(公告)号：US08417503B2
公开(公告)日：2013-04-09
申请号：US10023235
申请日：2001-12-17
申请人： Kerry Bernstein , Josef S. Watts , Richard Q. Williams
发明人： Kerry Bernstein , Josef S. Watts , Richard Q. Williams
IPC分类号： G06F17/50 , G06F9/455 , G06F11/30 , G06F19/00
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A method and structure for a computer model of a device has a performance parameter. The performance parameter includes a first bounded range and a second bounded range. The first bounded range has performance parameter variations within a single manufacturing process, and the second bounded range has performance parameter variations of different device designs.

8. 发明授权

US08119474B2 High performance capacitors in planar back gates CMOS 有权
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US08119474B2
公开(公告)日：2012-02-21
申请号：US12688243
申请日：2010-01-15
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

9. 发明授权

US07572724B2 Doped single crystal silicon silicided eFuse 有权
标题翻译：掺杂单晶硅硅片eFuse
公开(公告)号：US07572724B2
公开(公告)日：2009-08-11
申请号：US12043226
申请日：2008-03-06
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/00
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

10. 发明申请

US20080303139A1 CHIP-IN-SLOT INTERCONNECT FOR 3D CHIP STACKS 失效
标题翻译：用于3D芯片堆叠的插槽插槽互连
公开(公告)号：US20080303139A1
公开(公告)日：2008-12-11
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

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