专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07659844B2 Optical-to-electrical converter and analog-to-digital converter thereof 有权
标题翻译：光电转换器及其模 - 数转换器
公开(公告)号：US07659844B2
公开(公告)日：2010-02-09
申请号：US11962094
申请日：2007-12-21
申请人： Hung-Wei Tseng , Ling-Chang Hu , Shi-Hsiang Lu , Wein-Town Sun
发明人： Hung-Wei Tseng , Ling-Chang Hu , Shi-Hsiang Lu , Wein-Town Sun
IPC分类号： H03M1/56
CPC分类号： H03M1/54
摘要： An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.
摘要翻译：公开了一种用于将光信号转换为电信号的模数转换器（ADC）。 ADC包括检测模块，第一P型金属氧化物半导体（PMOS）晶体管，第一N型金属氧化物半导体（NMOS）晶体管，第一开关单元和输出模块。第一PMOS晶体管和第一NMOS晶体管形成反相器。第一开关单元设置在逆变器的输入端子和输出端子之间，并根据第一控制信号导通/截止。输出模块耦合到逆变器的输出端子，用于对输入电压大于参考电压的时间进行计数并产生数字信号。

2. 发明申请

US20090028570A1 OPTICAL-TO-ELECTRICAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTER THEREOF 有权
标题翻译：光电转换器及其模拟数字转换器
公开(公告)号：US20090028570A1
公开(公告)日：2009-01-29
申请号：US11962094
申请日：2007-12-21
申请人： Hung-Wei Tseng , Ling-Chang Hu , Shi-Hsiang Lu , Wein-Town Sun
发明人： Hung-Wei Tseng , Ling-Chang Hu , Shi-Hsiang Lu , Wein-Town Sun
IPC分类号： H04B10/00 , H03M1/12
CPC分类号： H03M1/54
摘要： An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.
摘要翻译：公开了一种用于将光信号转换为电信号的模数转换器（ADC）。 ADC包括检测模块，第一P型金属氧化物半导体（PMOS）晶体管，第一N型金属氧化物半导体（NMOS）晶体管，第一开关单元和输出模块。第一PMOS晶体管和第一NMOS晶体管形成反相器。第一开关单元设置在逆变器的输入端子和输出端子之间，并根据第一控制信号导通/截止。输出模块耦合到逆变器的输出端子，用于对输入电压大于参考电压的时间进行计数并产生数字信号。

3. 发明授权

US06628548B1 Flash memory with accelerated transient state transitions 有权
标题翻译：具有加速瞬态状态转换的闪存
公开(公告)号：US06628548B1
公开(公告)日：2003-09-30
申请号：US10248044
申请日：2002-12-12
申请人： Yu-Ming Hsu , Ling-Chang Hu
发明人： Yu-Ming Hsu , Ling-Chang Hu
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： A non-volatile memory unit includes memory units for providing a data current corresponding to stored data; a first load unit having a first end; a second load unit having a second end; and a sensing unit. The first load unit and the second load unit can receive current input to build voltages respectively at the first end and the second end. When the memory unit provides the data current, the second load unit is enabled such that the data current inputs into the first load unit and the second load unit; then the second load is disabled after a predetermined time such that the data current inputs into the first load unit only, and the sensing unit generates a data signal for data-acquisition according to a voltage difference between the voltage at the first end and a reference voltage.
摘要翻译：非易失性存储器单元包括用于提供与存储的数据相对应的数据电流的存储器单元; 具有第一端的第一负载单元; 具有第二端的第二负载单元; 和感测单元。第一负载单元和第二负载单元可以接收电流输入以分别在第一端和第二端构建电压。当存储单元提供数据电流时，第二负载单元被使能使得数据电流输入到第一负载单元和第二负载单元; 那么在预定时间之后禁用第二负载，使得数据电流仅输入到第一负载单元中，并且感测单元根据第一端的电压和基准之间的电压差产生用于数据采集的数据信号电压。

4. 发明授权

US08659090B2 Resistive memory and methods for forming the same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US08659090B2
公开(公告)日：2014-02-25
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

5. 发明申请

US20130161707A1 Resistive Memory and Methods for Forming the Same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US20130161707A1
公开(公告)日：2013-06-27
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式