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1. 发明授权

US5945352A Method for fabrication of shallow isolation trenches with sloped wall profiles 失效
标题翻译：用于制造具有倾斜壁型材的浅隔离沟槽的方法
公开(公告)号：US5945352A
公开(公告)日：1999-08-31
申请号：US994710
申请日：1997-12-19
申请人： Hung-Sheng Chen , Mark S. Chang
发明人： Hung-Sheng Chen , Mark S. Chang
IPC分类号： H01L21/308 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76237 , H01L21/3085 , H01L21/3086 , H01L21/76232 , Y10S148/05
摘要： The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.
摘要翻译：本发明提供一种用于在半导体晶片中制造具有倾斜壁的浅隔离沟槽的方法。该方法使用共形多晶硅层在半导体衬底中的沟槽区域上形成蚀刻势垒。该蚀刻屏障具有不同厚度的区域。蚀刻阻挡层的最厚区域位于沟槽结构的边缘上并减缓下面的衬底中的蚀刻过程。蚀刻阻挡层的较薄区域不会将蚀刻过程阻碍到很大的程度。该蚀刻速率差异导致倾斜的沟槽壁轮廓。通过用介电材料填充表面然后平坦化来完成隔离沟槽。

2. 发明授权

US07973709B2 Electronic device for decoding navigation data by using phase angle variation and method thereof 有权
标题翻译：用于通过使用相位角变化对导航数据进行解码的电子设备及其方法
公开(公告)号：US07973709B2
公开(公告)日：2011-07-05
申请号：US12413799
申请日：2009-03-30
申请人： Hung-Sheng Chen
发明人： Hung-Sheng Chen
IPC分类号： G01S19/23 , G01S19/21 , G01S19/54
CPC分类号： G01S19/27
摘要： An electronic device for decoding a navigation data by using a phase angle variation and a method thereof are described, which includes the following steps. A phase angle difference between the first phase angle of the first navigation data and the second phase angle of the second navigation data from a satellite signal is calculated. When the phase angle difference is greater than 90 degrees, the first navigation data and the second navigation data are determined to have opposite signs. The second navigation data according to the first navigation data and the result is determined. Therefore, each data is interpreted through directly comparing whether the phase angle difference with the previous data is greater than 90 degrees or not, so that the correct rate in decoding the navigation data is increased.
摘要翻译：描述了通过使用相位角变化对导航数据进行解码的电子设备及其方法，其包括以下步骤。计算第一导航数据的第一相位角与来自卫星信号的第二导航数据的第二相位角之间的相位角差。当相位角差大于90度时，第一导航数据和第二导航数据被确定为具有相反的符号。确定根据第一导航数据和结果的第二导航数据。因此，通过直接比较相位角差与先前数据是否大于90度来解释每个数据，从而增加对解码导航数据的正确速率。

3. 发明授权

US07884761B2 Method for tracking satellite signal by GPS 有权
标题翻译：通过GPS跟踪卫星信号的方法
公开(公告)号：US07884761B2
公开(公告)日：2011-02-08
申请号：US12429732
申请日：2009-04-24
申请人： Hung-Sheng Chen
发明人： Hung-Sheng Chen
IPC分类号： G01S19/24 , G01S19/29 , G01S19/30 , G01S19/37
CPC分类号： G01S19/29 , G01S19/27
摘要： A method for tracking a satellite signal by a GPS includes the following steps. Data is continuously received from one of satellites by using tracking frequencies updated one by one based on an average phase difference of received data. Phase inversion points in the plurality of received data are interpreted. A time difference between each two adjacent phase inversion points among the phase inversion points is calculated. It is determined whether each time difference is an integral multiple of 20 ms. When each time difference is an integral multiple of 20 ms, 1-bit data is retrieved for every 20 ms from the satellite signal by taking a first phase inversion point among the plurality of phase inversion points as a starting point. Thus, a positioning speed is increased and a required positioning time is reduced by finding out a precise tracking frequency and a correct phase inversion point.
摘要翻译：用GPS跟踪卫星信号的方法包括以下步骤。通过使用基于接收数据的平均相位差逐个更新的跟踪频率，从卫星之一连续地接收数据。解释多个接收数据中的相位反转点。计算相位反转点之间的每两个相邻相位反转点之间的时间差。确定每个时间差是否为20ms的整数倍。当每个时间差是20ms的整数倍时，通过以多个相位反转点中的第一相位反转点为起点，从卫星信号每20ms检索1位数据。因此，通过找出精确的跟踪频率和正确的相位转换点，增加定位速度并减少所需的定位时间。

4. 发明授权

US06660585B1 Stacked gate flash memory cell with reduced disturb conditions 有权
标题翻译：具有减少干扰条件的堆叠式门闪存单元
公开(公告)号：US06660585B1
公开(公告)日：2003-12-09
申请号：US09531787
申请日：2000-03-21
申请人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , G11C16/0416 , H01L21/28273
摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.
摘要翻译：在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

5. 发明授权

US06444530B1 Process for fabricating an integrated circuit with a self-aligned contact 有权
标题翻译：用于制造具有自对准接触的集成电路的工艺
公开(公告)号：US06444530B1
公开(公告)日：2002-09-03
申请号：US09318429
申请日：1999-05-25
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L2924/0002 , Y10T428/12542 , Y10T428/1259 , Y10T428/12625 , Y10T428/12778 , H01L2924/00
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
摘要翻译：在闪速存储器件中形成触点的方法利用局部互连处理技术。局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。接触可以包括钨。堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

6. 发明授权

US06232646B1 Shallow trench isolation filled with thermal oxide 失效
标题翻译：浅沟隔离填充热氧化物
公开(公告)号：US06232646B1
公开(公告)日：2001-05-15
申请号：US09082607
申请日：1998-05-20
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2900
CPC分类号： H01L21/7621 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

7. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

8. 发明申请

US20100164799A1 ELECTRONIC DEVICE AND METHOD FOR SEARCHING SATELLITES 有权
标题翻译：电子设备和搜索卫星的方法
公开(公告)号：US20100164799A1
公开(公告)日：2010-07-01
申请号：US12424734
申请日：2009-04-16
申请人： Hung-Sheng Chen
发明人： Hung-Sheng Chen
IPC分类号： G01S1/00
CPC分类号： G01S19/28 , G01S19/42
摘要： A method for searching satellites includes obtaining a position information, obtaining a time information, calculating a regional range according to the position information, finding out numbers of target satellites corresponding to the time information and within the regional range from ephemeris data in an ephemeris database, searching the target satellites corresponding to the numbers, and receiving the satellite signals from each searched target satellite. In an electronic device capable of searching satellites, an operation interface is used to output the position information, and a calculation unit is used to calculate the regional range according to the received position information. A look-up unit is electrically connected to the ephemeris database, and used to find out the numbers of the target satellites corresponding to time information and within the regional range from the ephemeris data.
摘要翻译：一种用于搜索卫星的方法包括：获取位置信息，获取时间信息，根据位置信息计算区域范围，从星历数据库中的星历数据中查找与时间信息对应的目标卫星的数目，并在区域范围内，搜索与该号码对应的目标卫星，并从每个搜索到的目标卫星接收卫星信号。在能够搜索卫星的电子设备中，使用操作界面输出位置信息，并且使用计算单元根据接收到的位置信息来计算区域范围。查询单元与星历数据库电连接，用于从星历数据中查找与时间信息对应的目标卫星的数量，并在区域范围内。

9. 发明申请

US20100164794A1 METHOD FOR OBTAINING PRECISE INTERMEDIATE FREQUENCY OF GLOBAL POSITIONING SYSTEM (GPS) 有权
标题翻译：获取全球定位系统（GPS）精密中频的方法
公开(公告)号：US20100164794A1
公开(公告)日：2010-07-01
申请号：US12406683
申请日：2009-03-18
申请人： Hung-Sheng Chen
发明人： Hung-Sheng Chen
IPC分类号： G01S5/14 , H04B7/185
CPC分类号： G01S19/29
摘要： A method for obtaining a precise intermediate frequency for a global positioning system (GPS) is applied in a GPS receiver having a radio frequency (RF) module. Using a satellite signal received by the RF module, ephemeris data of a satellite is completely obtained, and present coordinate of the GPS receiver is calculated. First coordinate of the satellite at first time point and second coordinate of the satellite at second time point are calculated using the ephemeris data. Then, traveling speed of the satellite and projection value of the traveling speed on position vector from the first coordinate to the present coordinate are calculated using the first time point, the first coordinate, the second time point, and the second coordinate. Finally, the precise intermediate frequency is calculated using the signal frequency, a carrier frequency of the satellite, the projection value, and velocity of light.
摘要翻译：在具有射频（RF）模块的GPS接收机中应用用于获得全球定位系统（GPS）的精确中频的方法。使用由RF模块接收的卫星信号，完全获得卫星的星历数据，并计算GPS接收机的当前坐标。使用星历数据计算卫星在第一时间点的卫星的第一坐标和第二时间点的卫星的第二坐标。然后，使用第一时间点，第一坐标，第二时间点和第二坐标来计算卫星的行驶速度和从第一坐标到当前坐标的位置矢量上的行驶速度的投影值。最后，使用信号频率，卫星的载波频率，投影值和光速计算精确的中频。

10. 发明授权

US06841846B1 Antifuse structure and a method of forming an antifuse structure 有权
标题翻译：防腐结构和形成反熔丝结构的方法
公开(公告)号：US06841846B1
公开(公告)日：2005-01-11
申请号：US10625491
申请日：2003-07-22
申请人： Hung-Sheng Chen , Huan-Chung Tseng , Chang-Kai Huang
发明人： Hung-Sheng Chen , Huan-Chung Tseng , Chang-Kai Huang
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present invention comprises a plurality of layers, the first being a lower electrode that is disposed on an impurity region in a semiconductor substrate. A dielectric layer is disposed on the lower electrode, wherein the dielectric layer has a planar surface. A non-conductive hemispherical grain (HSG) layer is formed on the planar surface of the dielectric layer and an upper electrode is disposed on said non-conductive hemispherical grain (HSG) layer forming the antifuse.
摘要翻译：本发明包括具有半球纹（HSG）层的反熔丝以及形成具有半球纹（HSG）层的反熔丝的方法。本发明的反熔丝包括多个层，第一层是设置在半导体衬底的杂质区上的下电极。电介质层设置在下电极上，其中电介质层具有平坦表面。在电介质层的平坦表面上形成非导电半球形晶粒（HSG）层，并且在形成反熔丝的所述非导电半球形晶粒（HSG）层上设置上电极。

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