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1. 发明申请

US20100027394A1 SERVO CALIBRATION MARK DETECTION CIRCUIT FOR HD-DVD OR DVD-RAM AND METHOD THEREOF 审中-公开
标题翻译：用于HD-DVD或DVD-RAM的SERVO校准标记检测电路及其方法
公开(公告)号：US20100027394A1
公开(公告)日：2010-02-04
申请号：US12577829
申请日：2009-10-13
申请人： Hung-Chieh Tsai , Yu-Hsuan Lin , Hsiang-Ji Hsieh
发明人： Hung-Chieh Tsai , Yu-Hsuan Lin , Hsiang-Ji Hsieh
IPC分类号： G11B27/36
CPC分类号： G11B7/0956 , G11B7/00736
摘要： The invention provides a servo calibration mark detection circuit for use in an optical disk drive. In one embodiment, the servo calibration mark detection circuit comprises a summing processor, a slicing level generator, and a comparator. The summing processor sums an intensity of a light beam reflected from both an inner groove and an outer groove to obtain a first signal. The slicing level generator generates a slicing level. The comparator then compares the first signal with the slicing level to obtain a second signal, wherein the second signal indicates a first location of a first servo calibration mark recorded on the inner groove and a second location of a second servo calibration mark recorded on the outer groove.
摘要翻译：本发明提供一种用于光盘驱动器的伺服校准标记检测电路。在一个实施例中，伺服校准标记检测电路包括求和处理器，限幅电平发生器和比较器。求和处理器将从内槽和外槽两者反射的光束的强度相加以获得第一信号。切片电平发生器产生切片电平。比较器然后将第一信号与限幅电平进行比较以获得第二信号，其中第二信号指示记录在内槽上的第一伺服校准标记的第一位置和记录在外槽上的第二伺服校准标记的第二位置槽。

2. 发明申请

US20070280060A1 SERVO CALIBRATION MARK DETECTION CIRCUIT FOR HD-DVD OR DVD-RAM AND METHOD THEREOF 审中-公开
标题翻译：用于HD-DVD或DVD-RAM的SERVO校准标记检测电路及其方法
公开(公告)号：US20070280060A1
公开(公告)日：2007-12-06
申请号：US11752447
申请日：2007-05-23
申请人： Hung-Chieh Tsai , Yu-Hsuan Lin , Hsiang-Ji Hsieh
发明人： Hung-Chieh Tsai , Yu-Hsuan Lin , Hsiang-Ji Hsieh
IPC分类号： G11B7/00
CPC分类号： G11B7/0956 , G11B7/00736
摘要： The invention provides a servo calibration mark detection circuit for use in an optical disk drive. In one embodiment, the servo calibration mark detection circuit comprises a summing processor, a slicing level generator, and a comparator. The summing processor sums an intensity of a light beam reflected from both an inner groove and an outer groove to obtain a first signal. The slicing level generator generates a slicing level. The comparator then compares the first signal with the slicing level to obtain a second signal, wherein the second signal indicates a first location of a first servo calibration mark recorded on the inner groove and a second location of a second servo calibration mark recorded on the outer groove.
摘要翻译：本发明提供一种用于光盘驱动器的伺服校准标记检测电路。在一个实施例中，伺服校准标记检测电路包括求和处理器，限幅电平发生器和比较器。求和处理器将从内槽和外槽两者反射的光束的强度相加以获得第一信号。切片电平发生器产生切片电平。比较器然后将第一信号与限幅电平进行比较以获得第二信号，其中第二信号指示记录在内槽上的第一伺服校准标记的第一位置和记录在外槽上的第二伺服校准标记的第二位置槽。

3. 发明授权

US08890611B2 Operational amplifier circuits 有权
标题翻译：运算放大器电路
公开(公告)号：US08890611B2
公开(公告)日：2014-11-18
申请号：US13612784
申请日：2012-09-12
申请人： Hung-Chieh Tsai , Chi-Lun Lo , Chen-Yen Ho , Yu-Hsin Lin
发明人： Hung-Chieh Tsai , Chi-Lun Lo , Chen-Yen Ho , Yu-Hsin Lin
IPC分类号： H03F3/45 , H03F3/193 , H03F1/14 , H03F1/32 , H03F3/30
CPC分类号： H03F3/45179 , H03F1/14 , H03F1/3211 , H03F1/483 , H03F3/193 , H03F3/3023 , H03F3/45 , H03F3/45076 , H03F3/45188 , H03F2200/36 , H03F2203/45222 , H03F2203/45521 , H03F2203/45526 , H03F2203/45626
摘要： An operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
摘要翻译：运算放大器电路包括第一级放大器电路，第二级放大器电路和第一前馈电路。第一级放大器电路耦合到第一输入节点，用于接收第一输入信号并放大第一输入信号以产生第一放大信号。第二级放大器电路耦合到第一级放大器电路，用于接收第一放大信号并放大第一放大信号以在第一输出节点产生第一输出信号。第一前馈电路耦合在第一输入节点和第二级放大器电路之间，用于将第一输入信号向前馈送到第二级放大器电路。

4. 发明授权

US08344921B2 Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method 有权
标题翻译：具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法
公开(公告)号：US08344921B2
公开(公告)日：2013-01-01
申请号：US13072797
申请日：2011-03-28
申请人： Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
发明人： Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M3/412 , H03M3/426 , H03M7/3042
摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.
摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。截断器接收数字信息并根据数字信息产生截断的信息。反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

5. 发明申请

US20110181334A1 TRACK AND HOLD CIRCUIT AND RELATED RECEIVING DEVICE WITH TRACK AND HOLD CIRCUIT EMPLOYED THEREIN 有权
标题翻译：跟踪和保持电路跟踪和相关接收设备跟踪并保持已使用的电路
公开(公告)号：US20110181334A1
公开(公告)日：2011-07-28
申请号：US12695164
申请日：2010-01-28
申请人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
发明人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
IPC分类号： H03L5/00
CPC分类号： H03G3/3052 , H03G1/0088
摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
摘要翻译：运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。

6. 发明授权

US07652878B2 Modular computer housing 有权
标题翻译：模块化电脑外壳
公开(公告)号：US07652878B2
公开(公告)日：2010-01-26
申请号：US11590939
申请日：2006-10-31
申请人： Hung-Chieh Tsai
发明人： Hung-Chieh Tsai
IPC分类号： H05K5/00 , H05K7/00 , G06F1/20 , A47B81/00
CPC分类号： G06F1/183
摘要： A computer housing includes a main housing, a mounting frame, and a first cover. The main housing defines an accommodation space adapted to receive a motherboard module and a data-reading device therein. The mounting frame is disposed removably within the main housing, and is adapted to be mounted with the data-reading device thereon. The first cover is attached openably and closably to the main housing, and is disposed in proximity to the mounting frame for covering a top end of the accommodation space in the main housing. A first notch in the main housing is aligned with a second notch in the first cover such that the first and second notches form cooperatively an opening aligned with a disk slot in the data-reading device.
摘要翻译：计算机壳体包括主壳体，安装框架和第一盖板。主壳体限定适于在其中接收主板模块和数据读取装置的容纳空间。安装框架可移除地设置在主壳体内，并且适于在其上安装数据读取装置。第一盖可开启地并且可靠地附接到主壳体，并且设置在安装框架附近，以覆盖主壳体中的容纳空间的顶端。主壳体中的第一凹口与第一盖中的第二凹口对准，使得第一和第二凹口与数据读取装置中的盘槽配合地形成开口。

7. 发明申请

US20090237150A1 BANDGAP REFERENCE CIRCUIT WITH LOW OPERATING VOLTAGE 有权
标题翻译：具有低工作电压的带宽参考电路
公开(公告)号：US20090237150A1
公开(公告)日：2009-09-24
申请号：US12051989
申请日：2008-03-20
申请人： Hung-Chieh Tsai , Yu-Hsin Lin
发明人： Hung-Chieh Tsai , Yu-Hsin Lin
IPC分类号： G05F1/10 , H03F3/16
CPC分类号： H03F3/45183 , G05F3/30 , H03F3/345 , H03F2200/456
摘要： A bandgap reference circuit comprising a current mirror, an operational amplifier, first and second BJT transistors is disclosed. The current mirror comprises a first input terminal, a second input terminal and at least one output terminal. The operational amplifier is coupled to the current mirror, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have a zero or near zero threshold voltage. The first and second BJT transistors are coupled to two input terminals of the operational amplifier respectively, wherein at least one of the first and second BJT transistors is coupled to the output terminal of the current mirror through a conductive path.
摘要翻译：公开了一种带隙参考电路，其包括电流镜，运算放大器，第一和第二BJT晶体管。电流镜包括第一输入端，第二输入端和至少一个输出端。运算放大器耦合到电流镜，其中分别耦合到第一和第二输入端的第一晶体管和第二晶体管具有零或接近零的阈值电压。第一和第二BJT晶体管分别耦合到运算放大器的两个输入端，其中第一和第二BJT晶体管中的至少一个通过导电路径耦合到电流镜的输出端。

8. 发明授权

US08149047B2 Bandgap reference circuit with low operating voltage 有权
标题翻译：带隙参考电路，工作电压低
公开(公告)号：US08149047B2
公开(公告)日：2012-04-03
申请号：US12051989
申请日：2008-03-20
申请人： Hung-Chieh Tsai , Yu-Hsin Lin
发明人： Hung-Chieh Tsai , Yu-Hsin Lin
IPC分类号： G05F3/02
CPC分类号： H03F3/45183 , G05F3/30 , H03F3/345 , H03F2200/456
摘要： A bandgap reference circuit comprising a current mirror, an operational amplifier, first and second BJT transistors is disclosed. The current mirror comprises a first input terminal, a second input terminal and at least one output terminal. The operational amplifier is coupled to the current mirror, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have a zero or near zero threshold voltage. The first and second BJT transistors are coupled to two input terminals of the operational amplifier respectively, wherein at least one of the first and second BJT transistors is coupled to the output terminal of the current mirror through a conductive path.
摘要翻译：公开了一种带隙参考电路，其包括电流镜，运算放大器，第一和第二BJT晶体管。电流镜包括第一输入端，第二输入端和至少一个输出端。运算放大器耦合到电流镜，其中分别耦合到第一和第二输入端的第一晶体管和第二晶体管具有零或接近零的阈值电压。第一和第二BJT晶体管分别耦合到运算放大器的两个输入端，其中第一和第二BJT晶体管中的至少一个通过导电路径耦合到电流镜的输出端。

9. 发明申请

US20090126789A1 Dye-sensitized solar cell 审中-公开
标题翻译：染料敏化太阳能电池
公开(公告)号：US20090126789A1
公开(公告)日：2009-05-21
申请号：US12289541
申请日：2008-10-30
申请人： Chung-Hua Li , Hung-Chieh Tsai
发明人： Chung-Hua Li , Hung-Chieh Tsai
IPC分类号： H01L31/00
CPC分类号： H01G9/2068 , H01G9/2031 , H01G9/2059 , H01G9/209 , Y02E10/542
摘要： The present invention relates to a dye-sensitized solar cell that exhibits improved photoabsorption efficiency and optoelectronic conversion efficiency in the long-wavelength region. The dye-sensitized solar cell of the present invention, in coordination with an outer loop, comprises: a first substrate; a second substrate; and a photoenergy conversion layer disposed between the first substrate and the second substrate. Herein, the photoenergy conversion layer comprises an electrolytic condensed matter and pluralities of dye-adsorbed units dispersed in the electrolytic condensed matter. In addition, a first photonic crystal layer is disposed on the surface of the first substrate. A beam of light from the external environment can pass through the first photonic crystal layer and the first substrate to arrive in the photoenergy conversion layer. The photoenergy conversion layer can convert the photoenergy of the light to electric energy and the outer loop electrically connects to the first substrate and the second substrate.
摘要翻译：本发明涉及在长波长区域显示出改进的光吸收效率和光电转换效率的染料敏化太阳能电池。本发明的染料敏化太阳能电池与外环配合，包括：第一衬底; 第二基板; 以及设置在第一基板和第二基板之间的光能转换层。这里，光能转换层包含电解浓缩物质和分散在电解浓缩物质中的多个吸附染料的单元。此外，第一光子晶体层设置在第一基板的表面上。来自外部环境的光束可以通过第一光子晶体层和第一衬底以到达光能转换层。光能转换层可以将光的光能转换成电能，而外环与第一衬底和第二衬底电连接。

10. 发明授权

US08638250B2 Amplifier, fully-differential amplifier and delta-sigma modulator 有权
标题翻译：放大器，全差分放大器和Δ-Σ调制器
公开(公告)号：US08638250B2
公开(公告)日：2014-01-28
申请号：US13590491
申请日：2012-08-21
申请人： Chen-Yen Ho , Chi-Lun Lo , Hung-Chieh Tsai , Yu-Hsin Lin
发明人： Chen-Yen Ho , Chi-Lun Lo , Hung-Chieh Tsai , Yu-Hsin Lin
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F3/265 , H03F3/30 , H03F3/3023 , H03F3/45071 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/18 , H03F2203/30021 , H03F2203/30033 , H03F2203/45022 , H03F2203/45134 , H03F2203/45138 , H03M3/39 , H03M3/50
摘要： An amplifier, a fully-differential amplifier and a delta-sigma modulator are disclosed. The disclosed amplifier includes a front-end gain stage, an AC-coupled push-pull output stage and a compensation circuit. The compensation circuit is coupled between the front-end gain stage and an output terminal of the amplifier. The AC-coupled push-pull output stage uses an AC-coupled capacitor (which is a passive two terminal electrical component rather than a stray or parasitic capacitance of a transistor) to couple the front-end gain stage to a gate of a top or bottom transistor of a push-pull structure introduced in the AC-coupled push-pull output stage, and uses a resistance component to couple a gate of the top or bottom transistor (depending on which one is coupled to the AC-coupled capacitor) to a bias voltage level.
摘要翻译：公开了放大器，全差分放大器和Δ-Σ调制器。所公开的放大器包括前端增益级，AC耦合推挽输出级和补偿电路。补偿电路耦合在前端增益级与放大器的输出端之间。交流耦合推挽输出级使用交流耦合电容器（其是无源双端电气元件而不是晶体管的杂散或寄生电容），以将前端增益级耦合到顶部的栅极或引入到AC耦合推挽输出级中的推挽结构的底部晶体管，并且使用电阻分量将顶部或底部晶体管的栅极（取决于耦合到AC耦合电容器的栅极）耦合到偏置电压电平。

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