专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07790553B2 Methods for forming high performance gates and structures thereof 失效
标题翻译：形成高性能栅极的方法及其结构
公开(公告)号：US07790553B2
公开(公告)日：2010-09-07
申请号：US12170687
申请日：2008-07-10
申请人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

2. 发明授权

US08053838B2 Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) 有权
标题翻译：应变鳍场效应晶体管的结构，制造方法，设计结构（FinFets）
公开(公告)号：US08053838B2
公开(公告)日：2011-11-08
申请号：US12146728
申请日：2008-06-26
申请人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
发明人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.
摘要翻译： FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。第一半导体种子区域包括第一半导体材料。第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。

3. 发明申请

US20090321828A1 STRUCTURES, FABRICATION METHODS, DESIGN STRUCTURES FOR STRAINED FIN FIELD EFFECT TRANSISTORS (FINFETS) 有权
标题翻译：结构，制造方法，应变金属场效应晶体管的设计结构（FINFETS）
公开(公告)号：US20090321828A1
公开(公告)日：2009-12-31
申请号：US12146728
申请日：2008-06-26
申请人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
发明人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.
摘要翻译： FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。第一半导体种子区域包括第一半导体材料。第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。

4. 发明申请

US20120139081A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：半导体绝缘体器件的应力发生结构
公开(公告)号：US20120139081A1
公开(公告)日：2012-06-07
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

5. 发明授权

US08115254B2 Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same 有权
标题翻译：绝缘体上半导体结构，包括含有绝缘体应力插头的沟槽及其制造方法
公开(公告)号：US08115254B2
公开(公告)日：2012-02-14
申请号：US11860851
申请日：2007-09-25
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

6. 发明授权

US08629501B2 Stress-generating structure for semiconductor-on-insulator devices 有权
标题翻译：绝缘体上半导体器件的应力产生结构
公开(公告)号：US08629501B2
公开(公告)日：2014-01-14
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

7. 发明申请

US20090079026A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：半导体绝缘体器件的应力发生结构
公开(公告)号：US20090079026A1
公开(公告)日：2009-03-26
申请号：US11860851
申请日：2007-09-25
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

8. 发明申请

US20080173942A1 STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE 审中-公开
标题翻译：具有应力硅化物的应变FinFET的结构和方法
公开(公告)号：US20080173942A1
公开(公告)日：2008-07-24
申请号：US11625431
申请日：2007-01-22
申请人： Huilong Zhu , Siddhartha Panda , Jay W. Strane , Sey-Ping Sun , Brian L. Tessier
发明人： Huilong Zhu , Siddhartha Panda , Jay W. Strane , Sey-Ping Sun , Brian L. Tessier
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A stressed semiconductor structure including at least one FinFET device on a surface of a substrate, typically a buried insulating layer of an initial semiconductor-on-insulator substrate, is provided. In a preferred embodiment, the at least one FinFET device includes a semiconductor Fin that is located on an unetched portion of the buried insulator layer which has a raised height as compared to an adjacent and adjoining etched portion of the buried insulating layer. The semiconductor Fin includes a gate dielectric on its sidewalls and optionally a hard mask located on an upper surface thereof. The inventive structure also includes a gate conductor, which is located on the surface of the substrate, typically the buried insulating layer, and the gate conductor is at least laterally adjacent to the gate dielectric located on the sidewalls of the semiconductor Fin. A stressed silicide is located on the gate conductor, which introduces stress into the channel of the FinFET device. The stressed silicide memorizes the stress from a sacrificial stressed film that is formed prior to forming the stressed silicide. The stress type of the stressed film is introduced into the silicide during a silicide anneal step.
摘要翻译：提供了一种应力半导体结构，其包括在衬底的表面上的至少一个FinFET器件，通常是初始绝缘体上半导体衬底的掩埋绝缘层。在优选实施例中，所述至少一个FinFET器件包括位于所述掩埋绝缘体层的未蚀刻部分上的半导体Fin，所述半导体Fin与所述掩埋绝缘层的相邻和相邻蚀刻部分相比具有升高的高度。半导体鳍包括其侧壁上的栅极电介质和任选地位于其上表面上的硬掩模。本发明的结构还包括栅极导体，其位于衬底的表面上，通常为掩埋绝缘层，并且栅极导体至少横向邻近位于半导体Fin的侧壁上的栅极电介质。应力硅化物位于栅极导体上，其将应力引入FinFET器件的沟道中。应力硅化物记忆在形成应力硅化物之前形成的牺牲应力膜的应力。在硅化物退火步骤期间，将应力膜的应力类型引入到硅化物中。

9. 发明申请

US20080169510A1 PERFORMANCE ENHANCEMENT ON BOTH NMOSFET AND PMOSFET USING SELF-ALIGNED DUAL STRESSED FILMS 审中-公开
标题翻译：使用自对准双应力膜的两个NMOSFET和PMOSFET的性能增强
公开(公告)号：US20080169510A1
公开(公告)日：2008-07-17
申请号：US11623871
申请日：2007-01-17
申请人： Mahender Kumar , Huilong Zhu
发明人： Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823412 , H01L27/088 , H01L27/092 , H01L29/7843
摘要： In an integrated circuit comprising both PMOSFETs and NMOSFETs, carrier mobility is enhanced on both types of FETs using dual stressed films. The adverse impact of having both layers of stressed films along the boundary between different types of films is eliminated by utilizing self-alignment of the edges of a second stressed film to a preexisting edge of a first stressed film. At the boundary between the two stressed films, one stressed film abuts another but no stressed film overlies another stressed film. By avoiding any overlap of stressed films, the stress exerted on the MOSFET channels is maximized.
摘要翻译：在包括PMOSFET和NMOSFET的集成电路中，使用双应力膜的两种类型的FET都增加了载流子迁移率。通过利用第二应力膜的边缘对第一应力膜的预先存在的边缘进行自对准，消除了沿不同类型的膜之间的边界具有两层应力膜的不利影响。在两个应力薄膜之间的边界处，一个应力薄膜邻接另一个，但没有应力薄膜覆盖另一个应力薄膜。通过避免应力膜的任何重叠，施加在MOSFET通道上的应力最大化。

10. 发明申请

US20080079037A1 FIELD EFFECT DEVICE INCLUDING INVERTED V SHAPED CHANNEL REGION AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：包括反相V形通道区域的场效应装置及其制造方法
公开(公告)号：US20080079037A1
公开(公告)日：2008-04-03
申请号：US11538174
申请日：2006-10-03
申请人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
发明人： Huilong Zhu , Ravikumar Ramachandran , Effendi Leobandung , Mahender Kumar , Wenjuan Zhu , Christine Norris
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/78648
摘要： A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped channel region. In another embodiment, the foregoing generally conventional gate electrode is used in conjunction with an inverted V shaped gate electrode that is located within an inverted V shaped notch that comprises the inverted V shaped channel region.
摘要翻译：半导体结构包括半导体层，其包括反向V形沟道区域，其允许避免半导体结构内的升高的源极/漏极区域。在一个实施例中，通常常规的栅电极位于反向V形沟道区上的半导体层的平面表面上方。在另一个实施例中，上述通常的常规栅极电极与位于包括反向V形沟道区域的倒V形凹口内的反向V形栅电极结合使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式