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1. 发明授权

US07385451B2 Arrangement, phase locked loop and method for noise shaping in a phase-locked loop 有权
标题翻译：锁相环的排列，锁相环和噪声整形方法
公开(公告)号：US07385451B2
公开(公告)日：2008-06-10
申请号：US10537634
申请日：2003-11-27
申请人： Hugues Beaulaton , Philippe Gorisse , Nadim Khlat
发明人： Hugues Beaulaton , Philippe Gorisse , Nadim Khlat
IPC分类号： H03L7/00
CPC分类号： H03M7/3022 , H03L7/1976
摘要： A noise shaping arrangement for a phase locked loop includes a first order sigma-delta modulator arranged to provide a first-order quantized output and a feedback path output. A second order sigma-delta modulator is arranged to receive the feedback path output and provides a second order quantized output. A combination block combines the first and second order quantized outputs to provide a combined third order quantized output, which provides noise shaping with a frequency notch spectrum. In this way a new quantization noise shape of third order is provided, such that quantization phase noise may be lowered, the PLL loop bandwidth may be increased, modulation phase error may be reduced and PLL locking speed increased.
摘要翻译：用于锁相环的噪声整形装置包括布置成提供一阶量化输出和反馈路径输出的一阶Σ-Δ调制器。第二级Σ-Δ调制器被布置成接收反馈路径输出并提供二阶量化输出。组合块组合了第一和第二阶量化输出以提供组合的三阶量化输出，其提供具有频率陷波频谱的噪声整形。以这种方式，提供三阶新的量化噪声形状，使得量化相位噪声可能降低，PLL环路带宽可能增加，调制相位误差可能降低，PLL锁定速度提高。

2. 发明申请

US20060192620A1 Arrangement, phase locked loop and method for noise shaping in a phase-locked loop 有权
标题翻译：锁相环的排列，锁相环和噪声整形方法
公开(公告)号：US20060192620A1
公开(公告)日：2006-08-31
申请号：US10537634
申请日：2003-11-27
申请人： Hugues Beaulaton , Philippe Gorisse , Nadim Khlat
发明人： Hugues Beaulaton , Philippe Gorisse , Nadim Khlat
IPC分类号： H03L7/085
CPC分类号： H03M7/3022 , H03L7/1976
摘要： A noise shaping arrangement for a phase locked loop includes a first order sigma-delta modulator (500) arranged to provide a first-order quantized output and a feedback path output (508). A second order sigma-delta modulator (520) is arranged to receive the feedback path output (508) and provides a second order quantized output. A combination block (530) combines the first and second order quantized outputs to provide a combined third order quantized output (540), which provides noise shaping with a frequency notch spectrum. In this way a new quantization noise shape of third order is provided, such that quantization phase noise may be lowered, the PLL loop bandwidth may be increased, modulation phase error may be reduced and PLL locking speed increased.
摘要翻译：用于锁相环的噪声整形装置包括布置成提供一阶量化输出和反馈路径输出（508）的第一级Σ-Δ调制器（500）。第二级Σ-Δ调制器（520）被布置成接收反馈路径输出（508）并提供二阶量化输出。组合块（530）组合第一和第二阶量化输出以提供组合的三阶量化输出（540），其提供具有频率陷波频谱的噪声整形。以这种方式，提供三阶新的量化噪声形状，使得量化相位噪声可能降低，PLL环路带宽可能增加，调制相位误差可能降低，PLL锁定速度提高。

3. 发明授权

US07880516B2 Method for noise reduction in a phase locked loop and a device having noise reduction capabilities 有权
标题翻译：锁相环中的降噪方法和具有降噪能力的装置
公开(公告)号：US07880516B2
公开(公告)日：2011-02-01
申请号：US11910062
申请日：2005-03-31
申请人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
发明人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/081 , H03L7/1976
摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.
摘要翻译：一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号和分频信号之间的差。一种包含锁相环的装置。锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

4. 发明申请

US20080265958A1 Method for Noise Reduction in a Phase Locked Loop and a Device Having Noise Reduction Capabilities 有权
标题翻译：一种锁相环路降噪方法及具有降噪能力的装置
公开(公告)号：US20080265958A1
公开(公告)日：2008-10-30
申请号：US11910062
申请日：2005-03-31
申请人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
发明人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/081 , H03L7/1976
摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.
摘要翻译：一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号与分频信号之间的差。一种包含锁相环的装置。锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

5. 发明申请

US20150185011A1 MICRO-ELECTRO-MECHANICAL SYSTEM DRIVE-MODE OSCILLATOR MODULE AND METHOD THEREFOR 有权
标题翻译：微电子机械系统驱动模式振荡器模块及其方法
公开(公告)号：US20150185011A1
公开(公告)日：2015-07-02
申请号：US14416727
申请日：2012-08-08
申请人： Hugues Beaulaton , Laurent Cornibert , Gerhard Trauth
发明人： Hugues Beaulaton , Laurent Cornibert , Gerhard Trauth
IPC分类号： G01C19/5712 , H03B28/00
CPC分类号： G01C19/5712 , G01C19/5776 , H03B28/00 , H03B2200/0082
摘要： A drive-mode oscillator module for use within a micro-electro-mechanical system (MEMS) device is described. The drive-mode oscillator module is arranged to receive a proof-mass measurement signal from a proof-mass of the MEMS device and to output a proof-mass actuation signal to the proof-mass of the MEMS device. The drive-mode oscillator module comprises a first, higher gain accuracy drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during an active mode of the MEMS device, and a second, lower power consumption drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during a standby mode of the MEMS device.
摘要翻译：描述了一种在微机电系统（MEMS）装置内使用的驱动模式振荡器模块。驱动模式振荡器模块被布置成从MEMS器件的校验质量接收校验质量测量信号，并将校验质量致动信号输出到MEMS器件的校准质量。所述驱动模式振荡器模块包括第一较高增益精度的驱动模式组件，用于在所述MEMS装置的有源模式期间产生由所述驱动模式振荡器模块输出的致动信号，以及第二低功耗驱动模式组件，模式分量，用于在MEMS装置的待机模式期间产生由驱动模式振荡器模块输出的致动信号。

6. 发明授权

US07605652B2 Loop gain equalizer for RF power amplifier 有权
标题翻译： RF功率放大器的环路增益均衡器
公开(公告)号：US07605652B2
公开(公告)日：2009-10-20
申请号：US12063012
申请日：2005-08-05
申请人： Hugues Beaulaton , Gerald Haennig , Didier Salle
发明人： Hugues Beaulaton , Gerald Haennig , Didier Salle
IPC分类号： H03G3/20
CPC分类号： H03F1/02 , H03F1/0272 , H03F2200/105 , H03F2200/78
摘要： The output power of an RF power amplifier is controlled using a feedback loop including a differential integrator for controlling the amplifier's bias voltage. The gain of integration in the differential integrator is varied so as to compensate for variations in the derivative of the power amplifier output power versus the bias voltage.
摘要翻译：使用包括用于控制放大器的偏置电压的差分积分器的反馈回路来控制RF功率放大器的输出功率。差分积分器的积分增益是变化的，以便补偿功率放大器输出功率相对于偏置电压的导数的变化。

7. 发明授权

US09166617B1 Communication unit, digital band-pass sigma-delta modulator and method therefor 有权
标题翻译：通信单元，数字带通Σ-Δ调制器及其方法
公开(公告)号：US09166617B1
公开(公告)日：2015-10-20
申请号：US14574568
申请日：2014-12-18
申请人： Hugues Beaulaton , Jean-Christophe Nanan
发明人： Hugues Beaulaton , Jean-Christophe Nanan
IPC分类号： H03M3/00 , H03K7/08 , H04L27/20 , H03G3/30
CPC分类号： H03M3/404 , H03G3/3042 , H03K7/08 , H03M3/30 , H03M3/402 , H03M3/502 , H03M7/3017 , H04L27/2092 , H04L27/368
摘要： A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch.
摘要翻译：通信单元包括功率DAC。 DAC包括：开关模式功率放大器（SMPA）; 以及可操作地耦合到SMPA的数字带通Σ-Δ调制器。 Σ-Δ调制器包括用于接收输入基带信号的输入端; 延迟; 加法器模块，被布置成将反馈信号与来自所述延迟的输出相加; 和至少两个反馈分支。 Σ-Δ调制器被布置为对输入基带信号进行数字过采样，使得由Σ-Δ调制器采用的采样频率与DAC输出的射频（RF）的比率是固定的，并且采样频率调谐或其中采样频率是固定的并且比率被调整，使得使用来自以下的组中的至少一个来形成Σ-Δ调制器中的第一反馈支路：零增益，第二反馈支路的加法逆。

8. 发明申请

US20160290804A1 IN-BAND BEATING REMOVAL FOR A MEMS GYROSCOPE 审中-公开
标题翻译：用于MEMS陀螺仪的带内去除
公开(公告)号：US20160290804A1
公开(公告)日：2016-10-06
申请号：US15035869
申请日：2013-11-22
申请人： Thierry CASSAGNES , Hugues BEAULATON , Laurent CORNIBERT , Yean Ling TEO
发明人： Thierry Cassagnes , Hugues Beaulaton , Laurent Cornibert , Yean Ling Teo
IPC分类号： G01C19/5726 , H04L7/033 , G06F1/08
CPC分类号： G01C19/5726 , G01C19/04 , G06F1/08 , G06F1/1694 , H04L7/033 , H04L7/06
摘要： A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS gyroscope (VMEMS). The circuitry comprises drive circuitry (DRIVE) arranged to drive, when the circuitry is connected, the vibration MEMS gyroscope (VMEMS) and a measurement unit (DMU) which provides a drive measurement voltage signal (DMV) forming a measure of a displacement of a mass along a drive axis. A sense circuitry (SENSE) is arranged to process a sense measurement signal of the vibration MEMS gyroscope (VMEMS) forming a measure for a displacement of the mass along a sense axis. A digital sample clock generator (SCG) is arranged to generate a sample clock signal (SCLK) from an input signal (FDxy) derivable from a drive measurement voltage signal (DMV). The sample clock generator (SCG) comprises an oscillator (HFOSC) arranged to generate a master clock (MOSC), and a counter unit (OSCCNTR) arranged to count master clock periods during one period of the input signal. The clock generator also comprises a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, and to compare the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit). A frequency shifter (FSH) will trigger the oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).
摘要翻译：振动陀螺仪电路（VCIRC）可连接到振动MEMS陀螺仪（VMEMS）。电路包括驱动电路（DRIVE），驱动电路（DRIVE）被布置成在电路连接时驱动振动MEMS陀螺仪（VMEMS）和测量单元（DMU），其提供驱动测量电压信号（DMV），其形成一个沿驱动轴的质量。感测电路（SENSE）被布置为处理振动MEMS陀螺仪（VMEMS）的感测测量信号，其形成沿着感测轴的质量位移的测量。数字采样时钟发生器（SCG）被布置成从可从驱动测量电压信号（DMV）导出的输入信号（FDxy）产生采样时钟信号（SCLK）。采样时钟发生器（SCG）包括布置成产生主时钟（MOSC）的振荡器（HFOSC）和被配置为在输入信号的一个周期期间对主时钟周期进行计数的计数器单元（OSCCNTR）。时钟发生器还包括一个数字计数监视器（NCM），用于确定在数量保持不变的多少个输入信号周期内，以及将常数周期数（Ncp）与临界数量的恒定周期（Ncp_crit）进行比较。每当数字监视（NCM）确定恒定周期数（Ncp）超过常数周期（Ncp_crit）的临界数时，移频器（FSH）将触发振荡器来移动主时钟频率。

9. 发明申请

US20130187719A1 PLL SYSTEM AND METHOD FOR CONTROLLING A GAIN OF A VCO CIRCUIT 有权
标题翻译：用于控制VCO电路的增益的PLL系统和方法
公开(公告)号：US20130187719A1
公开(公告)日：2013-07-25
申请号：US12936214
申请日：2008-04-18
申请人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
发明人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
IPC分类号： H03L7/16
CPC分类号： H03L7/16 , H03B5/1228 , H03B2201/0208 , H03L7/099 , H03L7/113 , H03L7/18
摘要： A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
摘要翻译：一种锁相环系统，包括：压控振荡器电路，包括第一多个可切换变容二极管，用于选择VCO的频带，其具有随频带变化的增益;以及第二多个可切换变容二极管，用于改变在所选频段的增益。 PLL系统具有PLL反馈电路，其包括用于将反馈电路切换到开环状态的开关装置，其中多个预定调谐电压可以施加到VCO; 用于测量合成VCO频率的频率测量装置; 以及控制单元，用于确定相对于合成频率和调谐电压的增益。

10. 发明授权

US09823074B2 Micro-electro-mechanical system drive-mode oscillator module and method therefor 有权
公开(公告)号：US09823074B2
公开(公告)日：2017-11-21
申请号：US14416727
申请日：2012-08-08
申请人： Hugues Beaulaton , Laurent Cornibert , Gerhard Trauth
发明人： Hugues Beaulaton , Laurent Cornibert , Gerhard Trauth
IPC分类号： G01C19/5712 , G01C19/5776 , H03B28/00
CPC分类号： G01C19/5712 , G01C19/5776 , H03B28/00 , H03B2200/0082
摘要： A drive-mode oscillator module for use within a micro-electro-mechanical system (MEMS) device is described. The drive-mode oscillator module is arranged to receive a proof-mass measurement signal from a proof-mass of the MEMS device and to output a proof-mass actuation signal to the proof-mass of the MEMS device. The drive-mode oscillator module comprises a first, higher gain accuracy drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during an active mode of the MEMS device, and a second, lower power consumption drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during a standby mode of the MEMS device.

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