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1. 发明授权

US08707232B2 Fault diagnosis based on design partitioning 有权
标题翻译：基于设计分区的故障诊断
公开(公告)号：US08707232B2
公开(公告)日：2014-04-22
申请号：US13492763
申请日：2012-06-08
申请人： Huaxing Tang , Wu-Tung J. Cheng , Robert Brady Benware , Xiaoxin Fan
发明人： Huaxing Tang , Wu-Tung J. Cheng , Robert Brady Benware , Xiaoxin Fan
IPC分类号： G06F17/50 , G06F11/00 , G01R31/00 , G06F11/26 , G06F11/263 , G01R31/28
CPC分类号： G06F17/5022 , G01R31/2803 , G01R31/2846 , G01R31/318357 , G06F11/261 , G06F11/263 , G06F17/505
摘要： Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.
摘要翻译：本发明的方面涉及基于电路设计划分的故障诊断技术。根据本发明的各种实施方式，故障芯片的电路设计首先划分为多个子电路。子电路可以基于观察点的扇形圆锥形成。共享门限比率可以用作将观测点的扇入锥添加到子电路中的度量。基于测试模式和子电路，确定子电路测试模式。然后在子电路上进行故障诊断。子电路故障诊断包括从故障模具的故障信息中提取子电路故障信息。子电路故障诊断可以对子电路中的边界门采用无故障值。

2. 发明申请

US20130024830A1 Fault Diagnosis Based On Design Partitioning 有权
标题翻译：基于设计分区的故障诊断
公开(公告)号：US20130024830A1
公开(公告)日：2013-01-24
申请号：US13492763
申请日：2012-06-08
申请人： Huaxing Tang , Wu-Tung J Cheng , Robert Brady Benware , Xiaoxin Fan
发明人： Huaxing Tang , Wu-Tung J Cheng , Robert Brady Benware , Xiaoxin Fan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/2803 , G01R31/2846 , G01R31/318357 , G06F11/261 , G06F11/263 , G06F17/505
摘要： Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.
摘要翻译：本发明的方面涉及基于电路设计划分的故障诊断技术。根据本发明的各种实施方式，故障芯片的电路设计首先划分为多个子电路。子电路可以基于观察点的扇形圆锥形成。共享门限比率可以用作将观测点的扇入锥添加到子电路中的度量。基于测试模式和子电路，确定子电路测试模式。然后在子电路上进行故障诊断。子电路故障诊断包括从故障模具的故障信息中提取子电路故障信息。子电路故障诊断可以对子电路中的边界门采用无故障值。

3. 发明申请

US20090183128A1 GENERATING TEST PATTERNS HAVING ENHANCED COVERAGE OF UNTARGETED DEFECTS 有权
标题翻译：生成有突出缺陷的增强测试模式
公开(公告)号：US20090183128A1
公开(公告)日：2009-07-16
申请号：US12404583
申请日：2009-03-16
申请人： Janusz Rajski , Huaxing Tang , Chen Wang
发明人： Janusz Rajski , Huaxing Tang , Chen Wang
IPC分类号： G06F17/50
CPC分类号： G01R31/31835 , G06F11/263
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于生成具有检测无目标缺陷的能力增加的测试图案的方法，装置和系统的代表性实施例。在一个示例性实施例中，例如，确定用于测试集成电路设计中的目标故障（例如，卡住故障或桥接故障）的一个或多个确定性测试值。确定在测试期间增加一个或多个非靶向缺陷的可检测性的附加测试值。创建一个或多个测试模式，其包括确定性测试值的至少一部分和附加测试值的至少一部分。还公开了包括用于使计算机执行任何公开的方法或包括由所公开的任何实施例产生的测试模式的计算机可执行指令的计算机可读介质。

4. 发明授权

US08812922B2 Speeding up defect diagnosis techniques 有权
标题翻译：加快缺陷诊断技术
公开(公告)号：US08812922B2
公开(公告)日：2014-08-19
申请号：US11688782
申请日：2007-03-20
申请人： Wei Zou , Huaxing Tang , Wu-Tung Cheng
发明人： Wei Zou , Huaxing Tang , Wu-Tung Cheng
IPC分类号： G01R31/28 , G06F11/00 , G06F11/22 , G06F11/26
CPC分类号： G01R31/3177 , G01R31/318342 , G06F11/2252 , G06F11/261
摘要： Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.
摘要翻译：故障诊断技术（例如效果原因诊断技术）可以通过例如使用相对较小的字典加速。本文描述的实施例将效果原因诊断的加速提高高达约160次。这些技术可用于通过测试响应压实机生成的压实故障数据来诊断缺陷。可以使用小尺寸的字典来减小故障候选列表的大小，并且还有助于选择用于模拟的通过模式的子集的过程。关键路径跟踪可用于处理具有较大数量故障位的故障模式，并且可以使用预先计算的小字典快速找到具有较少数量故障位的故障模式的初始候选。这里还描述了用于选择故障模拟的通过模式以识别电子电路中的故障的示例性技术。

5. 发明申请

US20090287438A1 Increased Fault Diagnosis Throughput Using Dictionaries For Hyperactive Faults 审中-公开
标题翻译：增加故障诊断吞吐量使用字典为超活动故障
公开(公告)号：US20090287438A1
公开(公告)日：2009-11-19
申请号：US12335453
申请日：2008-12-15
申请人： Wu-Tung Cheng , Huaxing Tang , Wei Zou , Manish Sharma
发明人： Wu-Tung Cheng , Huaxing Tang , Wei Zou , Manish Sharma
IPC分类号： G06F19/00
CPC分类号： G06F11/2252
摘要： Techniques to achieve greater diagnostic speeds using relatively small fault dictionaries, such as dictionaries that are only slightly larger than so-called NFB dictionaries. This speed-up may be achieved by identifying a set of faults called hyperactive faults, and creating a dictionary for identifying those faults.
摘要翻译：使用相对较小的故障字典来实现更高诊断速度的技术，例如仅比所谓的NFB字典略大的字典。这种加速可以通过识别一组称为多动故障的故障来实现，并创建用于识别这些故障的字典。

6. 发明申请

US20070226570A1 SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES 有权
标题翻译：加快缺陷诊断技术
公开(公告)号：US20070226570A1
公开(公告)日：2007-09-27
申请号：US11688782
申请日：2007-03-20
申请人： Wei Zou , Huaxing Tang , Wu-Tung Cheng
发明人： Wei Zou , Huaxing Tang , Wu-Tung Cheng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3177 , G01R31/318342 , G06F11/2252 , G06F11/261
摘要： Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.
摘要翻译：故障诊断技术（例如效果原因诊断技术）可以通过例如使用相对较小的字典加速。本文描述的实施例将效果原因诊断的加速提高高达约160次。这些技术可用于通过测试响应压实机生成的压实故障数据来诊断缺陷。可以使用小尺寸的字典来减小故障候选列表的大小，并且还有助于选择用于模拟的通过模式的子集的过程。关键路径跟踪可用于处理具有较大数量故障位的故障模式，并且可以使用预先计算的小字典快速找到具有较少数量故障位的故障模式的初始候选。这里还描述了用于选择故障模拟的通过模式以识别电子电路中的故障的示例性技术。

7. 发明授权

US08201131B2 Generating test patterns having enhanced coverage of untargeted defects 有权
标题翻译：生成具有增强的非目标缺陷覆盖度的测试模式
公开(公告)号：US08201131B2
公开(公告)日：2012-06-12
申请号：US12404583
申请日：2009-03-16
申请人： Janusz Rajski , Huaxing Tang , Chen Wang
发明人： Janusz Rajski , Huaxing Tang , Chen Wang
IPC分类号： G06F17/50
CPC分类号： G01R31/31835 , G06F11/263
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于生成具有检测无目标缺陷的能力增加的测试图案的方法，装置和系统的代表性实施例。在一个示例性实施例中，例如，确定用于测试集成电路设计中的目标故障（例如，卡住故障或桥接故障）的一个或多个确定性测试值。确定在测试期间增加一个或多个非靶向缺陷的可检测性的附加测试值。创建一个或多个测试模式，其包括确定性测试值的至少一部分和附加测试值的至少一部分。还公开了包括用于使计算机执行任何公开的方法或包括由所公开的任何实施例产生的测试模式的计算机可执行指令的计算机可读介质。

8. 发明申请

US20060066338A1 Fault dictionaries for integrated circuit yield and quality analysis methods and systems 有权
标题翻译：集成电路产品和质量分析方法和系统的故障字典
公开(公告)号：US20060066338A1
公开(公告)日：2006-03-30
申请号：US11221394
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G01R31/26
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.
摘要翻译：本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。例如，在一个示例性实施例中，生成用于从相应的观察点组合识别一个或多个缺陷候选的一个或多个故障字典。在该示例性方法中，观察点组合表示在应用相应测试图案时捕获故障测试值的被测电路的观察点。此外，一个实施例中的一个或多个故障字典通过以下方式产生：（a）对于第一缺陷候选，存储指示检测第一缺陷候选的测试图案的一个或多个第一指示符，以及（b）对于第二缺陷候选，存储指示检测第二缺陷候选的测试图案的至少第二指示符，第二指示符包括指示检测第一缺陷候选的哪个测试图案还检测第二缺陷候选的位掩码。

9. 发明授权

US07512508B2 Determining and analyzing integrated circuit yield and quality 有权
标题翻译：确定和分析集成电路产量和质量
公开(公告)号：US07512508B2
公开(公告)日：2009-03-31
申请号：US11221395
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G01R31/26 , G06F11/22
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
摘要翻译：本文公开了用于计算和分析集成电路产量和质量的方法，装置和系统。例如，在本文公开的一个示例性方法中，从设计用于电子设备中的功能使用的集成电路的处理测试响应接收信息。在该实施例中，该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际引起集成电路故障的概率。报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。

10. 发明授权

US07509600B2 Generating test patterns having enhanced coverage of untargeted defects 有权
标题翻译：生成具有增强的非目标缺陷覆盖度的测试模式
公开(公告)号：US07509600B2
公开(公告)日：2009-03-24
申请号：US10979496
申请日：2004-11-01
申请人： Janusz Rajski , Huaxing Tang , Chen Wang
发明人： Janusz Rajski , Huaxing Tang , Chen Wang
IPC分类号： G06F17/50
CPC分类号： G01R31/31835 , G06F11/263
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于生成具有检测无目标缺陷的能力增加的测试图案的方法，装置和系统的代表性实施例。在一个示例性实施例中，例如，确定用于测试集成电路设计中的目标故障（例如，卡住故障或桥接故障）的一个或多个确定性测试值。确定在测试期间增加一个或多个非靶向缺陷的可检测性的附加测试值。创建一个或多个测试模式，其包括确定性测试值的至少一部分和附加测试值的至少一部分。还公开了包括用于使计算机执行任何公开的方法或包括由所公开的任何实施例产生的测试模式的计算机可执行指令的计算机可读介质。

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