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1. 发明公开

EP3125248A1 LATCH AND D TRIGGER 审中-公开
标题翻译：锁定和触发
公开(公告)号：EP3125248A1
公开(公告)日：2017-02-01
申请号：EP14890156.4
申请日：2014-04-22
申请人： Huawei Technologies Co., Ltd.
发明人： MIAO, Xiangshui , LI, Yi , ZHOU, Yaxiong , XU, Ronggang , ZHAO, Junfeng , ZHANG, Shujie
IPC分类号： G11C11/00
CPC分类号： H03K3/35625 , G11C13/0002 , H03K3/0372
摘要： Embodiments of the present invention provide a latch and a D flip-flop. The latch includes: a switch, a resistive random-access memory, a bleeder circuit, and a voltage converter. When the switch is in an on state, the voltage converter is configured to output an output signal of the latch according to an input signal of the latch, where the output signal remains consistent with the input signal. When the switch changes from the on state to an off state, the resistive random-access memory is configured to work together with the bleeder circuit to enable an output signal of the latch when the switch is in the off state to remain consistent with an output signal of the latch when the switch is in the on state, thereby implementing a nonvolatile latching function. Because fewer components are used in the latch in the embodiments of the present invention, a circuit structure is simple, a circuit area is reduced, and integrity of an existing logic circuit can be improved.
摘要翻译：本发明的实施例提供一种锁存器和一个D触发器。锁存器包括：开关，电阻式随机存取存储器，泄放电路和电压转换器。当开关处于导通状态时，电压转换器被配置为根据锁存器的输入信号输出锁存器的输出信号，其中输出信号保持与输入信号一致。当开关从导通状态改变到关断状态时，电阻随机存取存储器被配置为与泄放电路一起工作，以在开关处于断开状态时使锁存器的输出信号与输出保持一致当开关处于导通状态时锁存器的信号，从而实现非易失性锁存功能。由于本发明实施例中锁存器使用的元件较少，因此电路结构简单，电路面积减小，可以提高现有逻辑电路的完整性。

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