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1. 发明授权

US07176481B2 In situ doped embedded sige extension and source/drain for enhanced PFET performance 有权
标题翻译：用于增强PFET性能的原位掺杂嵌入式扩展和源极/漏极
公开(公告)号：US07176481B2
公开(公告)日：2007-02-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译：公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

2. 发明授权

US07645656B2 Structure and method for making strained channel field effect transistor using sacrificial spacer 有权
标题翻译：使用牺牲隔离层制造应变通道场效应晶体管的结构和方法
公开(公告)号：US07645656B2
公开(公告)日：2010-01-12
申请号：US11463777
申请日：2006-08-10
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

3. 发明授权

US07135724B2 Structure and method for making strained channel field effect transistor using sacrificial spacer 有权
标题翻译：使用牺牲隔离层制造应变通道场效应晶体管的结构和方法
公开(公告)号：US07135724B2
公开(公告)日：2006-11-14
申请号：US10711637
申请日：2004-09-29
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

4. 发明申请

US20060065914A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
公开(公告)号：US20060065914A1
公开(公告)日：2006-03-30
申请号：US10711637
申请日：2004-09-29
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

5. 发明申请

US20060292779A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
标题翻译：使用真空间隔件制作应变通道场效应晶体管的结构和方法
公开(公告)号：US20060292779A1
公开(公告)日：2006-12-28
申请号：US11463777
申请日：2006-08-10
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L21/8234
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

6. 发明申请

US20060151837A1 IN SITU DOPED EMBEDDED SIGE EXTENSION AND SOURCE/DRAIN FOR ENHANCED PFET PERFORMANCE 有权
标题翻译：采用SITU DEDED嵌入式信号扩展和源/漏极增强PFET性能
公开(公告)号：US20060151837A1
公开(公告)日：2006-07-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry Utomo , Werner Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry Utomo , Werner Rausch
IPC分类号： H01L29/94
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译：公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

7. 发明授权

US08802965B2 Plasmonic nanocavity devices and methods for enhanced efficiency in organic photovoltaic cells 有权
标题翻译：等离子体纳米腔装置和有机光伏电池效率提高的方法
公开(公告)号：US08802965B2
公开(公告)日：2014-08-12
申请号：US12586383
申请日：2009-09-21
申请人： Nathan C. Lindquist , Wade A. Luhman , Russell J. Holmes , Sang-Hyun Oh
发明人： Nathan C. Lindquist , Wade A. Luhman , Russell J. Holmes , Sang-Hyun Oh
IPC分类号： H01L31/00
CPC分类号： H01L51/42 , B82Y10/00 , G02B5/008 , H01L51/0046 , H01L51/0078 , Y02E10/549 , Y02P70/521
摘要： Plasmonic nanocavity arrays and methods for enhanced efficiency in organic photovoltaic cells are described. Plasmonic nanocavities offer a promising and highly tunable alternative to conventional transparent conductors for photovoltaic applications using both organic and inorganic materials systems.
摘要翻译：描述了等离子体纳米腔阵列和用于提高有机光伏电池效率的方法。等离子体纳米结构为使用有机和无机材料系统的光伏应用的常规透明导体提供了有希望和高度可调的替代方案。

8. 发明申请

US20120161600A1 REPLICATION OF PATTERNED THIN-FILM STRUCTURES FOR USE IN PLASMONICS AND METAMATERIALS 有权
标题翻译：用于塑料和金属材料的图案薄膜结构的复制
公开(公告)号：US20120161600A1
公开(公告)日：2012-06-28
申请号：US13131197
申请日：2009-11-24
申请人： David J. Norris , Sang Eon Han , Aditya Bhan , Prashant Nagpal , Nathan Charles Lindquist , Sang-Hyun Oh
发明人： David J. Norris , Sang Eon Han , Aditya Bhan , Prashant Nagpal , Nathan Charles Lindquist , Sang-Hyun Oh
IPC分类号： H01J61/52 , B05D5/06 , B05D3/06 , B32B38/10
CPC分类号： H01L49/006 , B81C1/00119 , B81C99/009 , B82Y10/00 , B82Y40/00 , G02B1/002 , G02B5/008 , G02B6/1226 , G03F7/0002 , H01L31/02327 , H01L31/054 , H01L49/02 , Y02E10/52 , Y10T428/12486 , Y10T428/12493 , Y10T428/12507
摘要： The present invention provides templating methods for replicating patterned metal films from a template substrate such as for use in plasmonic devices and metamaterials. Advantageously, the template substrate is reusable and can provide plural copies of the structure of the template substrate. Because high-quality substrates that are inherently smooth and flat are available, patterned metal films in accordance with the present invention can advantageously provide surfaces that replicate the surface characteristics of the template substrate both in the patterned regions and in the unpatterned regions.
摘要翻译：本发明提供了用于从模板底物复制图案化金属膜的模板方法，例如用于等离子体激元装置和超材料。有利地，模板衬底是可重复使用的，并且可以提供模板衬底的结构的多个拷贝。因为本质上光滑平坦的高品质基板是可获得的，所以根据本发明的图案化金属膜可以有利地提供在图案化区域和未图案化区域中复制模板基板的表面特性的表面。

9. 发明授权

US06919212B2 Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor 有权
标题翻译：具有合并顶电极 - 平板电容器的铁电随机存取存储器件的制造方法
公开(公告)号：US06919212B2
公开(公告)日：2005-07-19
申请号：US10741670
申请日：2003-12-18
申请人： Sang-Hyun Oh , Kyu-Hyun Bang , In-Woo Jang , Jin-Yong Seong , Jin-Gu Kim , Song-Hee Park , Young-Ho Yang , Kye-Nam Lee , Suk-Kyoung Hong
发明人： Sang-Hyun Oh , Kyu-Hyun Bang , In-Woo Jang , Jin-Yong Seong , Jin-Gu Kim , Song-Hee Park , Young-Ho Yang , Kye-Nam Lee , Suk-Kyoung Hong
IPC分类号： H01L27/10 , H01L21/00 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.
摘要翻译：本发明涉及一种制造铁电随机存取存储器（FeRAM）器件的方法。该方法包括以下步骤：在衬底上形成第一层间绝缘层; 通过穿过所述第一层间绝缘层形成与所述基板的部分部分连接的存储节点接触件; 在所述第一层间绝缘层上形成连接到所述存储节点接点的下电极; 形成具有低于下电极的表面电平的第二层间绝缘层，使得第二层间绝缘层包围下电极的底部; 在所述第二层间绝缘层上形成包围所述下电极的上部的杂质扩散阻挡层; 在下电极和杂质扩散阻挡层上形成铁电层; 以及在所述铁电层上形成顶部电极。

10. 发明授权

US09401370B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09401370B2
公开(公告)日：2016-07-26
申请号：US13607243
申请日：2012-09-07
申请人： Sang-Moo Choi , Byung-Soo Park , Sang-Hyun Oh , Han-Soo Joo
发明人： Sang-Moo Choi , Byung-Soo Park , Sang-Hyun Oh , Han-Soo Joo
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L29/78 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/42324
摘要： A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate are disposed on sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.
摘要翻译：一种三维非易失性存储器件，其可以在使用栅极引入漏极泄漏（GIDL）电流的擦除操作期间提高擦除操作效率，以及用于制造三维非易失性存储器件的方法。非易失性存储器件包括形成在衬底上的沟道结构，所述衬底包括交替层叠的多个层间电介质层和多个沟道层，以及设置在第一层上的第一选择栅极和第二选择栅极侧和第二侧，其中第一选择栅极和第二选择栅极分别设置在多个沟道层的侧壁上，其中形成第一选择栅极的材料的功函数不同于功函数形成第二选择门的材料。

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