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1. 发明授权

US06463490B1 Dual data rate transfer on PCI bus 有权
标题翻译： PCI总线上的双数据速率传输
公开(公告)号：US06463490B1
公开(公告)日：2002-10-08
申请号：US09447724
申请日：1999-11-24
申请人： Hsuan-Yi Wang , Sheng-Chang Peng , Nai-Shung Chang
发明人： Hsuan-Yi Wang , Sheng-Chang Peng , Nai-Shung Chang
IPC分类号： G06F1312
CPC分类号： G06F13/423 , G06F13/4031
摘要： The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a read/write transaction, and during the read/write transaction, the request signal and the grant signal are idle. The method comprises the steps of: (a) driving a first ready signal by the PCI bus master; (b) driving a second read signal by the selected device in response to the first ready signal, which initiates the read/write transaction; (c) using the request signal and the grant signal as a data transfer strobe signal during the write and read transaction, respectively, the data transfer strobe signal has a plurality of clocks; and (d) performing the data transfers on rising and falling edges of the clocks of the data transfer strobe signal.
摘要翻译：本发明提供了一种在PCI总线主机和所选设备之间的PCI总线上执行数据传输的方法。其中，在PCI总线上存在用于读/写事务的请求信号和授权信号，并且在读/写事务期间，请求信号和授权信号是空闲的。该方法包括以下步骤：（a）由PCI总线主机驱动第一就绪信号; （b）响应于启动所述读/写交易的所述第一就绪信号，由所选择的设备驱动第二读信号; （c）分别在写入和读取事务期间使用请求信号和授权信号作为数据传输选通信号，数据传输选通信号具有多个时钟; 和（d）在数据传输选通信号的时钟的上升沿和下降沿执行数据传输。

2. 发明授权

US06484281B1 Software-based simulation system capable of simulating the combined functionality of a north bridge test module and a south bridge test module 有权
标题翻译：基于软件的仿真系统，能够模拟北桥测试模块和南桥测试模块的组合功能
公开(公告)号：US06484281B1
公开(公告)日：2002-11-19
申请号：US09459763
申请日：1999-12-13
申请人： Hsuan-Yi Wang , Jiin Lai , Nai-Shung Chang
发明人： Hsuan-Yi Wang , Jiin Lai , Nai-Shung Chang
IPC分类号： G01R3128
CPC分类号： G01R31/318342
摘要： A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.
摘要翻译：提供了一个基于软件的仿真系统，可以提供南桥测试模块和北桥测试模块的组合功能，该模块仅基于两个模块之一，即南桥测试模块或北桥测试模块，而不必使用两者。该基于软件的仿真系统的特征在于使用PCI主建模电路和PCI从属建模电路，其能够模拟北桥芯片组的功能，仅在南桥芯片组和北桥芯片组为包括在仿真系统中，并且在模拟系统中仅包括北桥芯片组且没有南桥芯片组的情况下，还能够模拟南桥芯片组的功能。

3. 发明授权

US07723843B2 Multi-package module and electronic device using the same 有权
标题翻译：多包装模块和使用电子装置的电子装置
公开(公告)号：US07723843B2
公开(公告)日：2010-05-25
申请号：US12354152
申请日：2009-01-15
申请人： Chih-Hsiung Lin , Nai-Shung Chang
发明人： Chih-Hsiung Lin , Nai-Shung Chang
IPC分类号： H01L23/34
CPC分类号： H01L23/367 , H01L23/3677 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15311 , H01L2924/15321
摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.
摘要翻译：一种用于多封装模块的封装衬底。封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。还公开了一种具有封装基板的电子器件。

4. 发明授权

US07525182B2 Multi-package module and electronic device using the same 有权
标题翻译：多包装模块和使用电子装置的电子装置
公开(公告)号：US07525182B2
公开(公告)日：2009-04-28
申请号：US11243121
申请日：2005-10-04
申请人： Chih-Hsiung Lin , Nai-Shung Chang
发明人： Chih-Hsiung Lin , Nai-Shung Chang
IPC分类号： H01L23/495
CPC分类号： H01L23/367 , H01L23/3677 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15311 , H01L2924/15321
摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.
摘要翻译：一种用于多封装模块的封装衬底。封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。还公开了一种具有封装基板的电子器件。

5. 发明申请

US20070288782A1 METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US20070288782A1
公开(公告)日：2007-12-13
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

6. 发明授权

US06946731B2 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 有权
公开(公告)号：US06946731B2
公开(公告)日：2005-09-20
申请号：US10173231
申请日：2002-06-14
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

7. 发明授权

US06944783B2 Power controller and associated multi-processor type supporting computer system 有权
标题翻译：电源控制器和相关的多处理器类型支持计算机系统
公开(公告)号：US06944783B2
公开(公告)日：2005-09-13
申请号：US10037896
申请日：2001-10-22
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.
摘要翻译：一种能够支持多种处理器类型的计算机系统的电源控制器。功率控制器接收来自微处理器的电压识别信号和来自母板的微处理器选择信号，以向微处理器提供正确的电压指定信号和端电压。本发明还向可以支持多种处理器类型的计算机系统的主板提供电压指定信号和端电压。

8. 发明申请

US20050033909A1 MOTHERBOARD UTILIZING A SINGLE-CHANNEL MEMORY CONTROLLER TO CONTROL MULTIPLE DYNAMIC RANDOM ACCESS MEMORIES 审中-公开
标题翻译：主机使用单通道记忆控制器控制多个动态随机存取记忆
公开(公告)号：US20050033909A1
公开(公告)日：2005-02-10
申请号：US10707106
申请日：2003-11-20
申请人： Nai-Shung Chang , Chunhung Chen , Wei Lee
发明人： Nai-Shung Chang , Chunhung Chen , Wei Lee
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1684
摘要： A motherboard utilizing a single-channel memory controller to control multiple DRAMs. The motherboard includes a first memory slot, a second memory slot, and a single-channel memory controller. The memory controller is connected to the first memory slot and the second memory slot respectively through a first bus and a second bus.
摘要翻译：使用单通道存储器控制器来控制多个DRAM的主板。主板包括第一存储器插槽，第二存储器插槽和单通道存储器控制器。存储器控制器分别通过第一总线和第二总线连接到第一存储器插槽和第二存储器插槽。

9. 发明授权

US06820219B1 Integrated testing method for concurrent testing of a number of computer components through software simulation 有权
标题翻译：集成测试方法，通过软件仿真同时测试多台计算机组件
公开(公告)号：US06820219B1
公开(公告)日：2004-11-16
申请号：US09621750
申请日：2000-07-21
申请人： Hsiang-Chou Huang , Jiin Lai , Nai-Shung Chang
发明人： Hsiang-Chou Huang , Jiin Lai , Nai-Shung Chang
IPC分类号： G06F1100
CPC分类号： G06F11/261 , G06F11/263
摘要： An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.
摘要翻译：提出了一种综合测试方法，通过软件仿真以多任务方式同时对多个计算机组件执行测试程序。在该方法中，首先执行初始化过程以指定模拟操作的总数，FIFO缓冲器大小，命令序列和操作的开始时间。这种集成测试方法的一个特征是测试程序以多任务方式并行执行所有被测组件，以响应命令序列中的每个命令进行操作。在被测试的两个或更多个组件竞争相同资源的情况下，仲裁器被激活以对这些竞争组件执行仲裁。

10. 发明授权

US06693451B2 Input/output buffer capable of supporting a multiple of transmission logic buses 有权
标题翻译：能够支持多路传输逻辑总线的输入/输出缓冲器
公开(公告)号：US06693451B2
公开(公告)日：2004-02-17
申请号：US10150812
申请日：2002-05-17
申请人： Jincheng Huang , Nai-Shung Chang , Yuangtsang Liaw
发明人： Jincheng Huang , Nai-Shung Chang , Yuangtsang Liaw
IPC分类号： H03K19003
CPC分类号： H03K19/018585
摘要： An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor signal to determine a particular kind of microprocessors used. According to the microprocessor being using, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various kinds of microprocessors.
摘要翻译：能够支持多种传输逻辑总线规格的输入/输出缓冲器。输入/输出缓冲器具有协调控制器，逻辑控制电路，第一晶体管，第二晶体管，第一电阻元件和第二电阻元件。逻辑控制电路拾取微处理器信号以确定使用的特定种类的微处理器。根据正在使用的微处理器，第一晶体管，第二晶体管，第一电阻元件和第二电阻元件的电导率被重新分配以适应微处理器的特定逻辑总线规格。因此，主电路板上的单个芯片组能够容纳各种微处理器。

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