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1. 发明授权

US06845052B1 Dual reference cell sensing scheme for non-volatile memory 有权
标题翻译：用于非易失性存储器的双参考单元感测方案
公开(公告)号：US06845052B1
公开(公告)日：2005-01-18
申请号：US10250040
申请日：2003-05-30
申请人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
发明人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C7/02
CPC分类号： G11C7/14 , G11C7/062 , G11C16/28 , G11C2207/2227
摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.
摘要翻译：本发明提供了一种用于非易失性存储器的双参考单元感测方案。高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

2. 发明授权

US06665216B1 Apparatus and system for reading non-volatile memory with dual reference cells 有权
标题翻译：用于读取具有双参考单元的非易失性存储器的装置和系统
公开(公告)号：US06665216B1
公开(公告)日：2003-12-16
申请号：US10202245
申请日：2002-07-23
申请人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Laing Chen , Wen-Chiao Ho , Ho-Chun Liou
发明人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Laing Chen , Wen-Chiao Ho , Ho-Chun Liou
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C7/062
摘要： A system for reading data in a memory cell includes three comparators, each of which has two inputs. A first reference cell having a low reference voltage is coupled to one input of the first comparator. A second reference cell having a high reference voltage is coupled to one input of the second comparator. A memory cell having a memory cell voltage is coupled to the other input of the first and second comparators. One input of the third comparator is coupled to the first comparator's output signal, which includes a difference voltage between the memory cell voltage and the low reference voltage. The other input of the third comparator is coupled to the second comparator's output signal, which includes a difference voltage between the memory cell voltage and the high reference voltage. A method and apparatus for reading data in a memory cell also are described.
摘要翻译：用于读取存储器单元中的数据的系统包括三个比较器，每个比较器具有两个输入。具有低参考电压的第一参考单元耦合到第一比较器的一个输入端。具有高参考电压的第二参考单元耦合到第二比较器的一个输入端。具有存储单元电压的存储单元耦合到第一和第二比较器的另一个输入端。第三比较器的一个输入耦合到第一比较器的输出信号，其包括存储单元电压和低参考电压之间的差电压。第三比较器的另一输入端耦合到第二比较器的输出信号，其包括存储单元电压和高参考电压之间的差电压。还描述了一种用于在存储器单元中读取数据的方法和装置。

3. 发明授权

US07649772B2 Memory and method for programming in multiple storage region multi-level cells 有权
标题翻译：用于在多个存储区域多级单元中编程的存储器和方法
公开(公告)号：US07649772B2
公开(公告)日：2010-01-19
申请号：US11779951
申请日：2007-07-19
申请人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.
摘要翻译：一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

4. 发明申请

US20090021994A1 MEMORY AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：用于编程其的存储器和方法
公开(公告)号：US20090021994A1
公开(公告)日：2009-01-22
申请号：US11779951
申请日：2007-07-19
申请人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.
摘要翻译：一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

5. 发明授权

US08270223B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08270223B2
公开(公告)日：2012-09-18
申请号：US12628710
申请日：2009-12-01
申请人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.
摘要翻译：存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。存储器扇区包括多个字线，每个字线耦合到多个存储器单元。选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。多个驱动器中的每一个耦合到多个字线中的一个。驱动器中的第一个被耦合到字线中的第一个以接收第一控制信号以传导第一字线和电压源，并且第二驱动器耦合到第二个字线以接收第二控制信号以将第二字线与电压源断开。

6. 发明申请

US20110085380A1 Method of Programming a Memory 有权
标题翻译：存储器编程方法
公开(公告)号：US20110085380A1
公开(公告)日：2011-04-14
申请号：US12970222
申请日：2010-12-16
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.
摘要翻译：一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。在编程方法的实施例中，对应的数据分别输入到数据缓冲器。对应于第n阶段的数据被编程到目标多级单元中。修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理根据第n个编程验证电压。重复上述步骤直到n等于最大值，n为正整数。

7. 发明申请

US20100054045A1 Memory and Reading Method Thereof 有权
标题翻译：记忆和阅读方法
公开(公告)号：US20100054045A1
公开(公告)日：2010-03-04
申请号：US12204009
申请日：2008-09-04
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C7/00
CPC分类号： G11C16/24 , G11C16/26
摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.
摘要翻译：存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。源极线耦合到目标存储器单元的第一端子。位线耦合到目标存储器单元的第二端子。读取控制电路用于选择性地向源极线施加工作电压。

8. 发明申请

US20090201060A1 CLOCK SYNCHRONIZING CIRCUIT 有权
标题翻译：时钟同步电路
公开(公告)号：US20090201060A1
公开(公告)日：2009-08-13
申请号：US12027285
申请日：2008-02-07
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K5/06 , H03K2005/00195
摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.
摘要翻译：提供了应用在SMD块中的时钟同步电路。时钟同步电路包括多个时钟同步单元级。时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生用于触发前级延迟单元各级的输出时钟的短脉冲。

9. 发明申请

US20080304337A1 METHOD FOR ACCESSING MEMORY 有权
标题翻译：访问存储器的方法
公开(公告)号：US20080304337A1
公开(公告)日：2008-12-11
申请号：US12174115
申请日：2008-07-16
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C11/5671
摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.
摘要翻译：提供了访问存储器的方法。存储器包括许多多级单元，每个单元具有至少一个能存储2n位的存储器，n是正整数。访问存储器的方法包括以下步骤：首先，将存储器的阈值电压分别定义为2n级，其中2n级中的每一级对应于n位的存储状态，存储状态的最高有效位为0级等级2n / 2-1对应于不同于2n / 2到2n-1级对应的存储状态的最高有效位。接下来，目标数据被分成n个部分，分割的目标数据被分别写入n个临时存储器。然后，将目标数据的n位写入多级单元。从n个临时存储器中的每一个收集n位数据中的每一个。

10. 发明授权

US08176373B2 Pre-code device, and pre-code system and pre-coding method thereof 有权
标题翻译：预代码装置及其预编码系统及其预编码方法
公开(公告)号：US08176373B2
公开(公告)日：2012-05-08
申请号：US13042910
申请日：2011-03-08
申请人： Chun-Hsiung Hung , Wen-Chiao Ho
发明人： Chun-Hsiung Hung , Wen-Chiao Ho
IPC分类号： G11C29/00
CPC分类号： G11C8/12 , G11C29/808
摘要： A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.
摘要翻译：预编码装置包括第一存储器电路，地址解码器和替代逻辑电路。第一存储器电路包括多个存储器块，并且在东部包括替换块。存储器块由多个相应的物理地址指向。替换块由替换地址指向。地址解码器解码输入地址以提供预代码地址。替代逻辑电路查找地址映射表，其将物理地址中的缺陷物理地址映射到替换地址，以在预代码地址对应于缺陷物理地址时将前缀地址映射到替换地址。替代逻辑电路相应地将代码前数据预编码到替换块。

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