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    • 3. 发明申请
    • CHIP PACKAGE
    • 芯片包装
    • US20110233770A1
    • 2011-09-29
    • US13070375
    • 2011-03-23
    • Hsin-Chih CHIUChia-Ming ChengChuan-Jin ShiuBai-Yao Lou
    • Hsin-Chih CHIUChia-Ming ChengChuan-Jin ShiuBai-Yao Lou
    • H01L23/498
    • H01L31/02164H01L27/14618H01L33/486H01L33/54H01L33/62H01L2224/13
    • A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.
    • 芯片封装包括:具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层,其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部,其中底部设置在开口中并与导电层电接触,并且上部位于开口的外侧,并沿远离 开口 从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层,在所述上部下方延伸,并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。